[llvm] [RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (PR #74993)

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git-clang-format --diff 2ca101f4b019adafe5fe3545420eaec160bd6e79 d885f279783fa588d90af2016653701233aab5a4 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d5aea7f0d5..97e9556294 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -357,7 +357,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                            ? Promote
                            : Expand);
 
-
   if (Subtarget.hasVendorXCVbitmanip()) {
     setOperationAction(ISD::BITREVERSE, XLenVT, Legal);
   } else {

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https://github.com/llvm/llvm-project/pull/74993