[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Craig Topper via llvm-commits]

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@@ -785,6 +785,22 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
   }
 
   // TODO: Non-GPR register classes.
+
+  if (RB.getID() == RISCV::VRBRegBankID) {
+    if (Ty.getSizeInBits().getKnownMinValue() <= 64) {
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topperc wrote:

Drop curly braces around single lines.

https://github.com/llvm/llvm-project/pull/74114