[llvm] 2b36d85 - [RISCV] Update comment for AVL operand in pseudo instructions. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-12-08T10:47:31-08:00
New Revision: 2b36d85a3e000793863c67d48880f23c1e6f95eb

URL: https://github.com/llvm/llvm-project/commit/2b36d85a3e000793863c67d48880f23c1e6f95eb
DIFF: https://github.com/llvm/llvm-project/commit/2b36d85a3e000793863c67d48880f23c1e6f95eb.diff

LOG: [RISCV] Update comment for AVL operand in pseudo instructions. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 127d3080491d1..5e06422cf9ada 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -81,9 +81,9 @@ def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
 def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
                               SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
 
-// Operand that is allowed to be a register or a 5 bit immediate.
-// This allows us to pick between VSETIVLI and VSETVLI opcodes using the same
-// pseudo instructions.
+// Operand that is allowed to be a register other than X0, a 5 bit unsigned
+// immediate, or -1. -1 means VLMAX. This allows us to pick between VSETIVLI and
+// VSETVLI opcodes using the same pseudo instructions.
 def AVL : RegisterOperand<GPRNoX0> {
   let OperandNamespace = "RISCVOp";
   let OperandType = "OPERAND_AVL";