[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 7 13:24:06 PST 2023

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https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/72340

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