[llvm] dd0e38e - [SLP]Add a test for missed insert_subvector pattern detection, NFC.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2023-12-07T10:46:14-08:00
New Revision: dd0e38eb3467c7ed3f15b31cb8771d5b2ce08675

URL: https://github.com/llvm/llvm-project/commit/dd0e38eb3467c7ed3f15b31cb8771d5b2ce08675
DIFF: https://github.com/llvm/llvm-project/commit/dd0e38eb3467c7ed3f15b31cb8771d5b2ce08675.diff

LOG: [SLP]Add a test for missed insert_subvector pattern detection, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
new file mode 100644
index 0000000000000..8e0f382222241
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux -pass-remarks-output=%t -mattr=+v -slp-threshold=-10 < %s | FileCheck %s
+; RUN: FileCheck %s --check-prefix=YAML < %t
+
+; YAML-LABEL: --- !Passed
+; YAML-NEXT:  Pass:            slp-vectorizer
+; YAML-NEXT:  Name:            StoresVectorized
+; YAML-NEXT:  Function:        test
+; YAML-NEXT:  Args:
+; YAML-NEXT:  - String:          'Stores SLP vectorized with cost '
+; YAML-NEXT:  - Cost:            '9'
+; YAML-NEXT:  - String:          ' and with tree size '
+; YAML-NEXT:  - TreeSize:        '7'
+
+define void @test() {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr null, align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = load float, ptr null, align 4
+; CHECK-NEXT:    [[TMP2:%.*]] = load float, ptr null, align 4
+; CHECK-NEXT:    [[V9IDX:%.*]] = getelementptr i8, ptr null, i32 4
+; CHECK-NEXT:    [[V14IDX:%.*]] = getelementptr i8, ptr null, i32 8
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <2 x float> [[TMP4]], float [[TMP2]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = fcmp ogt <2 x float> [[TMP3]], [[TMP5]]
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i1> [[TMP6]], i32 0
+; CHECK-NEXT:    [[V0_0:%.*]] = select i1 [[TMP7]], float [[TMP0]], float 0.000000e+00
+; CHECK-NEXT:    [[TMP8:%.*]] = select <2 x i1> [[TMP6]], <2 x float> [[TMP3]], <2 x float> zeroinitializer
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <2 x i1> [[TMP6]], i32 1
+; CHECK-NEXT:    [[V9_0:%.*]] = select i1 [[TMP9]], float [[TMP2]], float 0.000000e+00
+; CHECK-NEXT:    store float [[V0_0]], ptr null, align 4
+; CHECK-NEXT:    store float [[V9_0]], ptr [[V9IDX]], align 4
+; CHECK-NEXT:    store <2 x float> [[TMP8]], ptr [[V14IDX]], align 4
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = load float, ptr null, align 4
+  %1 = load float, ptr null, align 4
+  %2 = load float, ptr null, align 4
+  %cmp.i = fcmp ogt float %1, %0
+  %v14.0 = select i1 %cmp.i, float %1, float 0.000000e+00
+  %v0.0 = select i1 %cmp.i, float %0, float 0.000000e+00
+  %cmp4.i = fcmp ogt float 0.000000e+00, %2
+  %v19.0 = select i1 %cmp4.i, float 0.000000e+00, float 0.000000e+00
+  %v9.0 = select i1 %cmp4.i, float %2, float 0.000000e+00
+  store float %v0.0, ptr null, align 4
+  %v9idx = getelementptr i8, ptr null, i32 4
+  store float %v9.0, ptr %v9idx, align 4
+  %v14idx = getelementptr i8, ptr null, i32 8
+  store float %v14.0, ptr %v14idx, align 4
+  %v19idx = getelementptr i8, ptr null, i32 12
+  store float %v19.0, ptr %v19idx, align 4
+  ret void
+}