[llvm] 04cbfcc - [test][lsr] Add term-folding test cases with estimated trip counts
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 7 10:34:36 PST 2023
Author: Philip Reames
Date: 2023-12-07T10:34:29-08:00
New Revision: 04cbfcc33ae9a1bc440d553abc73b02421cf6ad2
URL: https://github.com/llvm/llvm-project/commit/04cbfcc33ae9a1bc440d553abc73b02421cf6ad2
DIFF: https://github.com/llvm/llvm-project/commit/04cbfcc33ae9a1bc440d553abc73b02421cf6ad2.diff
LOG: [test][lsr] Add term-folding test cases with estimated trip counts
Added:
Modified:
llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll b/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
index c9b66896eac785..0203abe69ac299 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
@@ -453,7 +453,7 @@ define void @non_branch_terminator(ptr %a) {
; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 4
; CHECK-NEXT: [[LSR_IV_NEXT3]] = add nsw i64 [[LSR_IV2]], -1
; CHECK-NEXT: switch i64 [[LSR_IV2]], label [[FOR_BODY]] [
-; CHECK-NEXT: i64 0, label [[FOR_END:%.*]]
+; CHECK-NEXT: i64 0, label [[FOR_END:%.*]]
; CHECK-NEXT: ]
; CHECK: for.end:
; CHECK-NEXT: ret void
@@ -473,3 +473,117 @@ for.body: ; preds = %for.body, %entry
for.end: ; preds = %for.body
ret void
}
+
+define void @expensive_expand_short_tc(ptr %a, i32 %offset, i32 %n) {
+; CHECK-LABEL: @expensive_expand_short_tc(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[A:%.*]], i64 84
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[OFFSET:%.*]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], 84
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP5]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[UGLYGEP2:%.*]], [[FOR_BODY]] ], [ [[UGLYGEP]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: store i32 1, ptr [[LSR_IV1]], align 4
+; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i32 [[OFFSET]]
+; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[UGLYGEP2]], [[SCEVGEP]]
+; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]], !prof [[PROF0:![0-9]+]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
+entry:
+ %uglygep = getelementptr i8, ptr %a, i64 84
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %lsr.iv1 = phi ptr [ %uglygep2, %for.body ], [ %uglygep, %entry ]
+ %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 0, %entry ]
+ store i32 1, ptr %lsr.iv1, align 4
+ %lsr.iv.next = add nsw i32 %lsr.iv, 1
+ %uglygep2 = getelementptr i8, ptr %lsr.iv1, i32 %offset
+ %exitcond.not = icmp eq i32 %lsr.iv.next, %n
+ br i1 %exitcond.not, label %for.end, label %for.body, !prof !{!"branch_weights", i32 1, i32 3}
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+define void @expensive_expand_long_tc(ptr %a, i32 %offset, i32 %n) {
+; CHECK-LABEL: @expensive_expand_long_tc(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[A:%.*]], i64 84
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[OFFSET:%.*]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], 84
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP5]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[UGLYGEP2:%.*]], [[FOR_BODY]] ], [ [[UGLYGEP]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: store i32 1, ptr [[LSR_IV1]], align 4
+; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i32 [[OFFSET]]
+; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[UGLYGEP2]], [[SCEVGEP]]
+; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]], !prof [[PROF1:![0-9]+]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
+entry:
+ %uglygep = getelementptr i8, ptr %a, i64 84
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %lsr.iv1 = phi ptr [ %uglygep2, %for.body ], [ %uglygep, %entry ]
+ %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 0, %entry ]
+ store i32 1, ptr %lsr.iv1, align 4
+ %lsr.iv.next = add nsw i32 %lsr.iv, 1
+ %uglygep2 = getelementptr i8, ptr %lsr.iv1, i32 %offset
+ %exitcond.not = icmp eq i32 %lsr.iv.next, %n
+ br i1 %exitcond.not, label %for.end, label %for.body, !prof !{!"branch_weights", i32 1, i32 300}
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+define void @expensive_expand_unknown_tc(ptr %a, i32 %offset, i32 %n) {
+; CHECK-LABEL: @expensive_expand_unknown_tc(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[A:%.*]], i64 84
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[OFFSET:%.*]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], 84
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP5]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[UGLYGEP2:%.*]], [[FOR_BODY]] ], [ [[UGLYGEP]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: store i32 1, ptr [[LSR_IV1]], align 4
+; CHECK-NEXT: [[UGLYGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i32 [[OFFSET]]
+; CHECK-NEXT: [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND:%.*]] = icmp eq ptr [[UGLYGEP2]], [[SCEVGEP]]
+; CHECK-NEXT: br i1 [[LSR_FOLD_TERM_COND_REPLACED_TERM_COND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
+entry:
+ %uglygep = getelementptr i8, ptr %a, i64 84
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %lsr.iv1 = phi ptr [ %uglygep2, %for.body ], [ %uglygep, %entry ]
+ %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 0, %entry ]
+ store i32 1, ptr %lsr.iv1, align 4
+ %lsr.iv.next = add nsw i32 %lsr.iv, 1
+ %uglygep2 = getelementptr i8, ptr %lsr.iv1, i32 %offset
+ %exitcond.not = icmp eq i32 %lsr.iv.next, %n
+ br i1 %exitcond.not, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
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