[lld] [RISCV] Compress unrelaxable lui when RVC attribute is present (PR #74715)

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git-clang-format --diff 3293c088c25db5be6042d20bd95c80a0863a88d0 058c918d265c724d77ed8bb0482eefcd6604bbab -- lld/ELF/Arch/RISCV.cpp
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View the diff from clang-format here.
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diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index eac835505b..ffe1ece274 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -662,8 +662,7 @@ static void relaxHi20Lo12(const InputSection &sec, size_t i, uint64_t loc,
     // and compressed instructions are enabled.
     // Try to compress the lui to a c.lui.
     const unsigned bits = config->wordsize * 8;
-    uint32_t rd =
-      extractBits(read32le(sec.content().data() + r.offset), 11, 7);
+    uint32_t rd = extractBits(read32le(sec.content().data() + r.offset), 11, 7);
     uint32_t newInsn = 0x6001 | (rd << 7); // c.lui
     int64_t imm = SignExtend64(r.sym->getVA(r.addend) + 0x800, bits) >> 12;
 

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https://github.com/llvm/llvm-project/pull/74715