[llvm] [X86][MC] Support Enc/Dec for EGPR for promoted MOVDIR instruction (PR #74713)

via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 7 04:16:20 PST 2023


github-actions[bot] wrote:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff 9ff7d0ebeb54347f9006405a6d08ed2b713bc411 39035d1ae56633c1dce88d7d2dcc2b6c31de116d -- llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/utils/TableGen/X86DisassemblerTables.cpp llvm/utils/TableGen/X86RecognizableInstr.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 23c5362e66..74d131e71a 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -879,8 +879,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
   for (unsigned index = 0; index < ATTR_max; ++index) {
     o.indent(i * 2);
 
-    if ((index & ATTR_EVEX) && (index & ATTR_64BIT) &&
-        (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
+    if ((index & ATTR_EVEX) && (index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
+        (index & ATTR_ADSIZE))
       o << "IC_EVEX_OPSIZE_ADSIZE";
     else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
       if (index & ATTR_EVEX)
@@ -902,7 +902,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
         o << "_XD";
       else if (index & ATTR_XS)
         o << "_XS";
-      
+
       if (index & ATTR_EVEX) {
         if (index & ATTR_EVEXKZ)
           o << "_KZ";
@@ -912,8 +912,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
         if (index & ATTR_EVEXB)
           o << "_B";
       }
-    }
-    else if ((index & ATTR_64BIT) && (index & ATTR_REX2))
+    } else if ((index & ATTR_64BIT) && (index & ATTR_REX2))
       o << "IC_64BIT_REX2";
     else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
       o << "IC_64BIT_REXW_XS";
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 06f2c63f4c..47ee9544f3 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -266,12 +266,11 @@ InstructionContext RecognizableInstr::insnContext() const {
     }
     // No L, no W
     else if (OpPrefix == X86Local::PD) {
-      if(AdSize == X86Local::AdSize32)
+      if (AdSize == X86Local::AdSize32)
         insnContext = IC_EVEX_OPSIZE_ADSIZE;
       else
         insnContext = EVEX_KB(IC_EVEX_OPSIZE);
-    }
-    else if (OpPrefix == X86Local::XD)
+    } else if (OpPrefix == X86Local::XD)
       insnContext = EVEX_KB(IC_EVEX_XD);
     else if (OpPrefix == X86Local::XS)
       insnContext = EVEX_KB(IC_EVEX_XS);

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https://github.com/llvm/llvm-project/pull/74713


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