[clang] [llvm] [mlir] [AMDGPU] - Add address space for strided buffers (PR #74471)

[Nicolai Hähnle via llvm-commits]

================
@@ -864,6 +865,17 @@ supported for the ``amdgcn`` target.
   (bits `127:96`). The specific interpretation of these fields varies by the
   target architecture and is detailed in the ISA descriptions.
 
+**Buffer Strided Pointer**
+  The buffer index pointer is an experimental address space. It is supposed to
+  model a 128-bit buffer descriptor and a 32-bit offset, like the **Buffer Fat
+  Pointer**. Additionally, it contains an index into the descriptor, which
+  allows the direct addressing of structured elements.
+
+  The buffer descriptor must be *raw*:
+  the stride is the size of a structured element, the "add tid" flag must be 0, the
+  swizzle eneable bits must be off, and the extent (NumRecords) must be measured in
----------------
nhaehnle wrote:

Typo: enable

Also, drop the part about the extent (NumRecords) -- that's not a requirement of the compiler, it's a requirement of the HW and should be implied by stating that the buffer descriptor is "raw". (And it is also incorrect on IIRC gfx8, which had NUM_RECORDS always in units of bytes)

https://github.com/llvm/llvm-project/pull/74471