[llvm] [AMDGPU] GFX12: select @llvm.prefetch intrinsic (PR #74576)

[Stanislav Mekhanoshin via llvm-commits]

================
@@ -959,6 +967,32 @@ def : GCNPat <
 }
 } // let OtherPredicates = [HasShaderCyclesRegister]
 
+def SIMM24bitPtr : ImmLeaf <iPTR,
+  [{return isInt<24>(Imm);}]
+>;
+
+multiclass SMPrefetchPat<string type, int cache_type> {
+  def : GCNPat <
+    (smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32 cache_type)),
+    (!cast<SM_Prefetch_Pseudo>("S_PREFETCH_"#type) $sbase, $offset, (i32 SGPR_NULL), (i8 0))
+  >;
+
+  def : GCNPat <
+    (smrd_prefetch (i64 SReg_64:$sbase), timm, timm, (i32 cache_type)),
+    (!cast<SM_Prefetch_Pseudo>("S_PREFETCH_"#type) $sbase, 0, (i32 SGPR_NULL), (i8 0))
+  >;
+
+  def : GCNPat <
+    (prefetch SIMM24bitPtr:$offset, timm, timm, (i32 cache_type)),
+    (!cast<SM_Prefetch_Pseudo>("S_PREFETCH_"#type#"_PC_REL") (as_i32timm $offset), (i32 SGPR_NULL), (i8 0))
+  > {
+    let AddedComplexity = 10;
+  }
----------------
rampitec wrote:

If you do not have pointer (essentially provide a null to the prefetch intrinsic as a base pointer) this pc_rel pattern will be used. It may have no value as a data prefetch, but makes sense as inst prefetch. Say if you want to prefetch a next page of code. Like this:

```
define amdgpu_ps void @prefetch_inst_pc_rel_offset() {
; GFX12-SDAG-LABEL: prefetch_inst_pc_rel_offset:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_prefetch_inst_pc_rel 0x80, null, 0
; GFX12-SDAG-NEXT:    s_endpgm
entry:
  %gep = getelementptr i8, ptr addrspace(4) null, i32 128
  tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 0)
  ret void
}
```

https://github.com/llvm/llvm-project/pull/74576