[llvm] [AMDGPU] Lazily emit waitcnts on function entry (PR #73122)

[Matt Arsenault via llvm-commits]

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@@ -292,6 +295,56 @@ class WaitcntBrackets {
     VgprVmemTypes[GprNo] = 0;
   }
 
+  void setNonEntryFunctionInitialState(const MachineFunction &MF) {
+    const MachineRegisterInfo &MRI = MF.getRegInfo();
+    const SIRegisterInfo &TRI = ST->getInstrInfo()->getRegisterInfo();
+
+    // All counters are in unknown states.
+    for (auto T : inst_counter_types())
+      setScoreUB(T, getWaitCountMax(T));
+
+    // There may be pending events of any type.
+    if (ST->hasVscnt()) {
+      setPendingEvent(VMEM_READ_ACCESS);
+      setPendingEvent(VMEM_WRITE_ACCESS);
+      setPendingEvent(SCRATCH_WRITE_ACCESS);
+    } else {
+      setPendingEvent(VMEM_ACCESS);
+    }
+    for (unsigned I = LDS_ACCESS; I < NUM_WAIT_EVENTS; ++I)
+      setPendingEvent(WaitEventType(I));
+
+    auto SetStateForPhysReg = [&](MCRegister Reg) {
+      RegInterval Interval = getRegInterval(Reg, &MRI, &TRI);
+      if (Interval.first < NUM_ALL_VGPRS) {
+        for (int RegNo = Interval.first; RegNo < Interval.second; ++RegNo) {
+          for (auto T : inst_counter_types())
+            setRegScore(RegNo, T, getWaitCountMax(T));
+          VgprVmemTypes[RegNo] = -1;
+        }
+      } else {
+        for (int RegNo = Interval.first; RegNo < Interval.second; ++RegNo)
+          setRegScore(RegNo, LGKM_CNT, getWaitCountMax(LGKM_CNT));
+      }
+    };
+
+    // Live-in registers may depend on any counter.
+    const MachineBasicBlock &EntryMBB = MF.front();
+    for (auto [Reg, Mask] : EntryMBB.liveins()) {
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arsenm wrote:

MRI.liveins is way less reliable. For example, we're missing verification that everything in it is mirrored in the entry block live ins. Additionally GlobalISel doesn't even populate it, and it's apparently not an issue

https://github.com/llvm/llvm-project/pull/73122