[llvm] [XCore] Set MaxAtomicSizeInBitsSupported to 0 (PR #74389)

[Nigel Perks via llvm-commits]

https://github.com/nigelp-xmos approved this pull request.

That's correct that XCore does not have atomicrmw or cmpxchg. It lowered aligned atomic load & store because under its hardware memory model they would be inherently atomic.

To check my understanding: within the max bits, we are expected to support all five atomic instructions. So currently aligned 4-byte atomicrmw (for example) crashes with isel error. But unaligned operations will already go to library. So if atomicrmw etc are not supported, load & store cannot be either.

Just to mention, while looking at this, I noticed that TargetLoweringBase.cpp has the comment that the default will be set to 0 - just wondered if that's still the case.

https://github.com/llvm/llvm-project/pull/74389