[llvm] eaba81f - [SDAG] Count call argument attributes to reduce unnecessary extension (#73501)
via llvm-commits
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Tue Dec 5 00:55:56 PST 2023
Author: ZengZhijin
Date: 2023-12-05T09:55:52+01:00
New Revision: eaba81fd245da952a2a708495bf97d7791e8b965
URL: https://github.com/llvm/llvm-project/commit/eaba81fd245da952a2a708495bf97d7791e8b965
DIFF: https://github.com/llvm/llvm-project/commit/eaba81fd245da952a2a708495bf97d7791e8b965.diff
LOG: [SDAG] Count call argument attributes to reduce unnecessary extension (#73501)
Count how often the value is with signext/zeroext calls
when determining the preferred extension type.
Added:
llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 1d0a03ccfcdc6..1128ecfd860db 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -64,11 +64,18 @@ static ISD::NodeType getPreferredExtendForValue(const Instruction *I) {
// can be exposed.
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
unsigned NumOfSigned = 0, NumOfUnsigned = 0;
- for (const User *U : I->users()) {
- if (const auto *CI = dyn_cast<CmpInst>(U)) {
+ for (const Use &U : I->uses()) {
+ if (const auto *CI = dyn_cast<CmpInst>(U.getUser())) {
NumOfSigned += CI->isSigned();
NumOfUnsigned += CI->isUnsigned();
}
+ if (const auto *CallI = dyn_cast<CallBase>(U.getUser())) {
+ if (!CallI->isArgOperand(&U))
+ continue;
+ unsigned ArgNo = CallI->getArgOperandNo(&U);
+ NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::ZExt);
+ NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::SExt);
+ }
}
if (NumOfSigned > NumOfUnsigned)
ExtendKind = ISD::SIGN_EXTEND;
diff --git a/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
new file mode 100644
index 0000000000000..bb65f408c77a5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
@@ -0,0 +1,119 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+ at PL_reg_match_utf8 = external global i8, align 1
+
+declare signext i32 @test1(i8 signext)
+
+declare signext i32 @test2(i8 signext)
+
+declare signext i32 @test3(i8 signext)
+
+define signext i32 @test() nounwind {
+; RV64I-LABEL: test:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a0, %hi(PL_reg_match_utf8)
+; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(a0)
+; RV64I-NEXT: beqz s0, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test1 at plt
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test2 at plt
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test3 at plt
+; RV64I-NEXT: j .LBB0_3
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: call test2 at plt
+; RV64I-NEXT: .LBB0_3:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+ %1 = load i8, ptr @PL_reg_match_utf8, align 1
+ %2 = icmp eq i8 %1, 0
+ br i1 %2, label %7, label %3
+
+3:
+ %4 = tail call signext i32 @test1(i8 signext %1)
+ %5 = tail call signext i32 @test2(i8 signext %1)
+ %6 = tail call signext i32 @test3(i8 signext %1)
+ br label %9
+
+7:
+ %8 = tail call signext i32 @test2(i8 signext 0)
+ br label %9
+
+9:
+ ret i32 0
+}
+
+
+define signext i32 @test_loop() nounwind {
+; RV64I-LABEL: test_loop:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li s1, -16
+; RV64I-NEXT: lui s2, %hi(PL_reg_match_utf8)
+; RV64I-NEXT: j .LBB1_2
+; RV64I-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test2 at plt
+; RV64I-NEXT: addiw s1, s1, 1
+; RV64I-NEXT: beqz s1, .LBB1_4
+; RV64I-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(s2)
+; RV64I-NEXT: beqz s0, .LBB1_1
+; RV64I-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test1 at plt
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test2 at plt
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call test3 at plt
+; RV64I-NEXT: addiw s1, s1, 1
+; RV64I-NEXT: bnez s1, .LBB1_2
+; RV64I-NEXT: .LBB1_4:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
+ br label %1
+
+1:
+ %2 = phi i32 [ 16, %0 ], [ %12, %11 ]
+ %3 = load i8, ptr @PL_reg_match_utf8, align 1
+ %4 = icmp eq i8 %3, 0
+ br i1 %4, label %9, label %5
+
+5:
+ %6 = tail call signext i32 @test1(i8 signext %3)
+ %7 = tail call signext i32 @test2(i8 signext %3)
+ %8 = tail call signext i32 @test3(i8 signext %3)
+ br label %11
+
+9:
+ %10 = tail call signext i32 @test2(i8 signext %3)
+ br label %11
+
+11:
+ %12 = add nsw i32 %2, -1
+ %13 = icmp eq i32 %12, 0
+ br i1 %13, label %14, label %1
+
+14:
+ ret i32 0
+}
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