[llvm] [AArch64] merge index address with large offset into base address (PR #72187)

[via llvm-commits]

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@@ -1069,6 +1069,42 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSigned
   return true;
 }
 
+// 16-bit optionally shifted immediates are legal for single mov.
+static bool isLegalSingleMOVImmediate(int64_t Immed) {
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vfdff wrote:

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https://github.com/llvm/llvm-project/pull/72187