[compiler-rt] 7e3aeee - [NFC][asan] Replace AsanInited/ENSURE_ASAN_INITED with TryAsanInitFromRtl (#74172)
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Mon Dec 4 14:56:25 PST 2023
Author: Vitaly Buka
Date: 2023-12-04T14:56:21-08:00
New Revision: 7e3aeee3bf515f5922b564d3a850ab9f933a32dd
URL: https://github.com/llvm/llvm-project/commit/7e3aeee3bf515f5922b564d3a850ab9f933a32dd
DIFF: https://github.com/llvm/llvm-project/commit/7e3aeee3bf515f5922b564d3a850ab9f933a32dd.diff
LOG: [NFC][asan] Replace AsanInited/ENSURE_ASAN_INITED with TryAsanInitFromRtl (#74172)
Added:
Modified:
compiler-rt/lib/asan/asan_interceptors.cpp
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/Mips/msa/basic_operations.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
llvm/test/CodeGen/X86/pr59980.ll
Removed:
################################################################################
diff --git a/compiler-rt/lib/asan/asan_interceptors.cpp b/compiler-rt/lib/asan/asan_interceptors.cpp
index a364b971bda8f..7f2aecae2e3a5 100644
--- a/compiler-rt/lib/asan/asan_interceptors.cpp
+++ b/compiler-rt/lib/asan/asan_interceptors.cpp
@@ -558,9 +558,8 @@ INTERCEPTOR(char *, strcpy, char *to, const char *from) {
INTERCEPTOR(char*, strdup, const char *s) {
void *ctx;
ASAN_INTERCEPTOR_ENTER(ctx, strdup);
- if (UNLIKELY(!AsanInited()))
+ if (UNLIKELY(!TryAsanInitFromRtl()))
return internal_strdup(s);
- ENSURE_ASAN_INITED();
uptr length = internal_strlen(s);
if (flags()->replace_str) {
ASAN_READ_RANGE(ctx, s, length + 1);
@@ -577,9 +576,8 @@ INTERCEPTOR(char*, strdup, const char *s) {
INTERCEPTOR(char*, __strdup, const char *s) {
void *ctx;
ASAN_INTERCEPTOR_ENTER(ctx, strdup);
- if (UNLIKELY(!AsanInited()))
+ if (UNLIKELY(!TryAsanInitFromRtl()))
return internal_strdup(s);
- ENSURE_ASAN_INITED();
uptr length = internal_strlen(s);
if (flags()->replace_str) {
ASAN_READ_RANGE(ctx, s, length + 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 69e3148b8c864..2a3425a42607e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -21006,18 +21006,20 @@ SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) {
&IsFast) ||
!IsFast)
return SDValue();
+ EVT PtrVT = Ptr.getValueType();
+ SDValue Offset =
+ DAG.getNode(ISD::MUL, DL, PtrVT, DAG.getZExtOrTrunc(Idx, DL, PtrVT),
+ DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT));
+ SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset);
MachinePointerInfo PointerInfo(ST->getAddressSpace());
// If the offset is a known constant then try to recover the pointer
// info
- SDValue NewPtr;
if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
unsigned COffset = CIdx->getSExtValue() * EltVT.getSizeInBits() / 8;
NewPtr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(COffset), DL);
PointerInfo = ST->getPointerInfo().getWithOffset(COffset);
- } else {
- NewPtr = TLI.getVectorElementPointer(DAG, Ptr, Value.getValueType(), Idx);
}
return DAG.getStore(Chain, DL, Elt, NewPtr, PointerInfo, ST->getAlign(),
diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll
index 1f6c430a932e0..fbae1bda7c665 100644
--- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll
+++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll
@@ -1879,7 +1879,6 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
; O32-NEXT: addu $1, $2, $25
; O32-NEXT: lw $2, %got(i32)($1)
; O32-NEXT: lw $2, 0($2)
-; O32-NEXT: andi $2, $2, 15
; O32-NEXT: lw $1, %got(v16i8)($1)
; O32-NEXT: addu $1, $1, $2
; O32-NEXT: jr $ra
@@ -1892,7 +1891,6 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
; N32-NEXT: lw $2, %got_disp(i32)($1)
; N32-NEXT: lw $2, 0($2)
-; N32-NEXT: andi $2, $2, 15
; N32-NEXT: lw $1, %got_disp(v16i8)($1)
; N32-NEXT: addu $1, $1, $2
; N32-NEXT: jr $ra
@@ -1904,8 +1902,7 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
; N64-NEXT: daddu $1, $1, $25
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
; N64-NEXT: ld $2, %got_disp(i32)($1)
-; N64-NEXT: lw $2, 0($2)
-; N64-NEXT: andi $2, $2, 15
+; N64-NEXT: lwu $2, 0($2)
; N64-NEXT: ld $1, %got_disp(v16i8)($1)
; N64-NEXT: daddu $1, $1, $2
; N64-NEXT: jr $ra
@@ -1928,7 +1925,6 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
; O32-NEXT: addu $1, $2, $25
; O32-NEXT: lw $2, %got(i32)($1)
; O32-NEXT: lw $2, 0($2)
-; O32-NEXT: andi $2, $2, 7
; O32-NEXT: lw $1, %got(v8i16)($1)
; O32-NEXT: lsa $1, $2, $1, 1
; O32-NEXT: jr $ra
@@ -1941,7 +1937,6 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
; N32-NEXT: lw $2, %got_disp(i32)($1)
; N32-NEXT: lw $2, 0($2)
-; N32-NEXT: andi $2, $2, 7
; N32-NEXT: lw $1, %got_disp(v8i16)($1)
; N32-NEXT: lsa $1, $2, $1, 1
; N32-NEXT: jr $ra
@@ -1953,8 +1948,7 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
; N64-NEXT: daddu $1, $1, $25
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
; N64-NEXT: ld $2, %got_disp(i32)($1)
-; N64-NEXT: lw $2, 0($2)
-; N64-NEXT: andi $2, $2, 7
+; N64-NEXT: lwu $2, 0($2)
; N64-NEXT: ld $1, %got_disp(v8i16)($1)
; N64-NEXT: dlsa $1, $2, $1, 1
; N64-NEXT: jr $ra
@@ -1977,7 +1971,6 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
; O32-NEXT: addu $1, $2, $25
; O32-NEXT: lw $2, %got(i32)($1)
; O32-NEXT: lw $2, 0($2)
-; O32-NEXT: andi $2, $2, 3
; O32-NEXT: lw $1, %got(v4i32)($1)
; O32-NEXT: lsa $1, $2, $1, 2
; O32-NEXT: jr $ra
@@ -1990,7 +1983,6 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
; N32-NEXT: lw $2, %got_disp(i32)($1)
; N32-NEXT: lw $2, 0($2)
-; N32-NEXT: andi $2, $2, 3
; N32-NEXT: lw $1, %got_disp(v4i32)($1)
; N32-NEXT: lsa $1, $2, $1, 2
; N32-NEXT: jr $ra
@@ -2002,8 +1994,7 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
; N64-NEXT: daddu $1, $1, $25
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
; N64-NEXT: ld $2, %got_disp(i32)($1)
-; N64-NEXT: lw $2, 0($2)
-; N64-NEXT: andi $2, $2, 3
+; N64-NEXT: lwu $2, 0($2)
; N64-NEXT: ld $1, %got_disp(v4i32)($1)
; N64-NEXT: dlsa $1, $2, $1, 2
; N64-NEXT: jr $ra
@@ -2027,7 +2018,6 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
; O32-NEXT: addu $1, $2, $25
; O32-NEXT: lw $2, %got(i32)($1)
; O32-NEXT: lw $2, 0($2)
-; O32-NEXT: andi $2, $2, 1
; O32-NEXT: lw $1, %got(v2i64)($1)
; O32-NEXT: lsa $1, $2, $1, 3
; O32-NEXT: sw $5, 4($1)
@@ -2041,7 +2031,6 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
; N32-NEXT: lw $2, %got_disp(i32)($1)
; N32-NEXT: lw $2, 0($2)
-; N32-NEXT: andi $2, $2, 1
; N32-NEXT: lw $1, %got_disp(v2i64)($1)
; N32-NEXT: lsa $1, $2, $1, 3
; N32-NEXT: jr $ra
@@ -2053,8 +2042,7 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
; N64-NEXT: daddu $1, $1, $25
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
; N64-NEXT: ld $2, %got_disp(i32)($1)
-; N64-NEXT: lw $2, 0($2)
-; N64-NEXT: andi $2, $2, 1
+; N64-NEXT: lwu $2, 0($2)
; N64-NEXT: ld $1, %got_disp(v2i64)($1)
; N64-NEXT: dlsa $1, $2, $1, 3
; N64-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
index 7e7b7403dbdfb..a3f41fd842222 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
@@ -321,13 +321,20 @@ define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {
}
define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) {
-; CHECK-LABEL: insertelt_v32i16_store:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andi a2, a2, 31
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: sh a1, 0(a0)
-; CHECK-NEXT: ret
+; RV32-LABEL: insertelt_v32i16_store:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a2, 1
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: sh a1, 0(a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: insertelt_v32i16_store:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a2, 32
+; RV64-NEXT: srli a2, a2, 31
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: sh a1, 0(a0)
+; RV64-NEXT: ret
%a = load <32 x i16>, ptr %x
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
store <32 x i16> %b, ptr %x
@@ -359,13 +366,20 @@ define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) {
}
define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) {
-; CHECK-LABEL: insertelt_v8f32_store:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andi a1, a1, 7
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: fsw fa0, 0(a0)
-; CHECK-NEXT: ret
+; RV32-LABEL: insertelt_v8f32_store:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a1, a1, 2
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: fsw fa0, 0(a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: insertelt_v8f32_store:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: srli a1, a1, 30
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: fsw fa0, 0(a0)
+; RV64-NEXT: ret
%a = load <8 x float>, ptr %x
%b = insertelement <8 x float> %a, float %y, i32 %idx
store <8 x float> %b, ptr %x
@@ -429,7 +443,6 @@ define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) {
define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
; RV32-LABEL: insertelt_v8i64_store:
; RV32: # %bb.0:
-; RV32-NEXT: andi a1, a1, 7
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: li a1, -1
@@ -439,8 +452,8 @@ define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
;
; RV64-LABEL: insertelt_v8i64_store:
; RV64: # %bb.0:
-; RV64-NEXT: andi a1, a1, 7
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: srli a1, a1, 29
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: li a1, -1
; RV64-NEXT: sd a1, 0(a0)
@@ -508,7 +521,6 @@ define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) {
define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
; RV32-LABEL: insertelt_c6_v8i64_store:
; RV32: # %bb.0:
-; RV32-NEXT: andi a1, a1, 7
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: sw zero, 4(a0)
@@ -518,8 +530,8 @@ define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
;
; RV64-LABEL: insertelt_c6_v8i64_store:
; RV64: # %bb.0:
-; RV64-NEXT: andi a1, a1, 7
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: srli a1, a1, 29
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: li a1, 6
; RV64-NEXT: sd a1, 0(a0)
diff --git a/llvm/test/CodeGen/X86/pr59980.ll b/llvm/test/CodeGen/X86/pr59980.ll
index a6d22c2244c89..0823f960724e2 100644
--- a/llvm/test/CodeGen/X86/pr59980.ll
+++ b/llvm/test/CodeGen/X86/pr59980.ll
@@ -9,7 +9,6 @@ define void @foo(ptr %0, ptr %1, ptr %2) #0 {
; CHECK: ## %bb.0:
; CHECK-NEXT: movl (%rdx), %eax
; CHECK-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0
-; CHECK-NEXT: andl $15, %eax
; CHECK-NEXT: vpextrw $0, %xmm0, (%rsi,%rax,2)
; CHECK-NEXT: retq
%4 = bitcast ptr %2 to ptr
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