[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Jiahan Xie via llvm-commits]

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@@ -240,6 +254,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
                                           : RISCV::GPRB32Idx];
 
+  unsigned VRBSize = getMaximumSize(RISCV::VRBRegBankID);
+  const ValueMapping *VRBValueMapping =
+      &RISCV::ValueMappings[VRBSize == 64 ? RISCV::VRB64Idx : RISCV::VRB32Idx];
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jiahanxie353 wrote:

Actually I'm a bit lost right now. Can I check my understanding?

1. 
> The size for VRB bank shouldn't change.

Does this refer to `unsigned VRBSize` never change?

2. Based on my understanding of your description, in [`PartMappings`](https://github.com/llvm/llvm-project/blob/c556c9c3792a322dfc3a9c60be9d7d32cf335235/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp#L27), I'll probably have:
```C++
    {0, 64, VRBRegBank}, // <= 64
    {0, 64, VRBRegBank}, {64, 128, VRBRegBank}, // 128, LMUL=2
    {0, 64, VRBRegBank}, {64, 128, VRBRegBank}, {128, 192, VRBRegBank}, {192, 256, VRBRegBank}, // 256, LMUL=4
    {0, 64, VRBRegBank} .... // 512, LMUL=8
```
?
And that I'll only have `PMI_VRB64` in [`PartialMappingIdx`](https://github.com/llvm/llvm-project/blob/c556c9c3792a322dfc3a9c60be9d7d32cf335235/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp#L34) since the size of VRB doesn't change?
And in [`ValueMapping`](https://github.com/llvm/llvm-project/blob/c556c9c3792a322dfc3a9c60be9d7d32cf335235/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp#L41), I'll probably have:
```C++
{&PartMappings[PMI_VRB64], 1},
{&PartMappings[PMI_VB64], 2},
{&PartMappings[PMI_VRB64], 4},
{&PartMappings[PMI_VRB64], 8}
```
?



https://github.com/llvm/llvm-project/pull/74114