[llvm] TargetInstrInfo, TargetSchedule: fix non-NFC parts of 9468de4 (PR #74338)

[Ramkumar Ramachandra via llvm-commits]

https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/74338

Follow up on a post-commit review of 9468de4 (TargetInstrInfo: make getOperandLatency return optional (NFC)) by Bjorn Pettersson to fix a couple of things that are not NFC:

- std::optional::operator<= returns true if the first operand is a std::nullopt. Fix a couple of places where we assumed it would return false.
- In TargetSchedule, computeInstrCost could take another codepath, returning InstrLatency instead of DefaultDefLatency. Fix one instance not accounting for this behavior.

>From 13933a63bd82c892b078a18469e7013d5ebb8a8e Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <Ramkumar.Ramachandra at imgtec.com>
Date: Mon, 4 Dec 2023 16:29:24 +0000
Subject: [PATCH] TargetInstrInfo, TargetSchedule: fix non-NFC parts of 9468de4

Follow up on a post-commit review of 9468de4 (TargetInstrInfo: make
getOperandLatency return optional (NFC)) by Bjorn Pettersson to fix a
couple of things that are not NFC:

- std::optional::operator<= returns true if the first operand is a
  std::nullopt. Fix a couple of places where we assumed it would return
  false.
- In TargetSchedule, computeInstrCost could take another codepath,
  returning InstrLatency instead of DefaultDefLatency. Fix one instance
  not accounting for this behavior.
---
 llvm/lib/CodeGen/TargetInstrInfo.cpp     | 2 +-
 llvm/lib/CodeGen/TargetSchedule.cpp      | 2 +-
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 4bd5c910b298d..4783742a14ad7 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1462,7 +1462,7 @@ bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
   unsigned DefClass = DefMI.getDesc().getSchedClass();
   std::optional<unsigned> DefCycle =
       ItinData->getOperandCycle(DefClass, DefIdx);
-  return DefCycle <= 1U;
+  return DefCycle && DefCycle <= 1U;
 }
 
 bool TargetInstrInfo::isFunctionSafeToSplit(const MachineFunction &MF) const {
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index a25d4ff78f4d9..ce59b096992d8 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -178,7 +178,7 @@ unsigned TargetSchedModel::computeOperandLatency(
   const unsigned DefaultDefLatency = TII->defaultDefLatency(SchedModel, *DefMI);
 
   if (!hasInstrSchedModel() && !hasInstrItineraries())
-    return InstrLatency;
+    return DefaultDefLatency;
 
   if (hasInstrItineraries()) {
     std::optional<unsigned> OperLatency;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 476a9bb15edbf..b85107ec47191 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -4836,7 +4836,7 @@ bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
     unsigned DefClass = DefMI.getDesc().getSchedClass();
     std::optional<unsigned> DefCycle =
         ItinData->getOperandCycle(DefClass, DefIdx);
-    return DefCycle <= 2U;
+    return DefCycle && DefCycle <= 2U;
   }
   return false;
 }