[llvm] [RISCV] Rework IDiv and FDiv pipes on SiFive7 (PR #73970)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 4 08:27:47 PST 2023
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/73970
>From 4e9928b81a1af34262e9c5776888f813db6e2452 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 4 Dec 2023 08:21:05 -0800
Subject: [PATCH 1/4] Precommit test case.
---
.../tools/llvm-mca/RISCV/SiFive7/div-fdiv.s | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
new file mode 100644
index 0000000000000..544872c259c8e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-u74 -timeline -iterations=1 < %s \
+# RUN: | FileCheck %s
+
+div a0, a1, a2
+fdiv.s f1, f2, f3
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 94
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.02
+# CHECK-NEXT: IPC: 0.02
+# CHECK-NEXT: Block RThroughput: 93.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 66 66.00 div a0, a1, a2
+# CHECK-NEXT: 1 27 27.00 fdiv.s ft1, ft2, ft3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFive7FDiv
+# CHECK-NEXT: [1] - SiFive7IDiv
+# CHECK-NEXT: [2] - SiFive7PipeA
+# CHECK-NEXT: [3] - SiFive7PipeB
+# CHECK-NEXT: [4] - SiFive7PipeV
+# CHECK-NEXT: [5] - SiFive7VA
+# CHECK-NEXT: [6] - SiFive7VL
+# CHECK-NEXT: [7] - SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: 26.00 65.00 - 93.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - 65.00 - 66.00 - - - - div a0, a1, a2
+# CHECK-NEXT: 26.00 - - 27.00 - - - - fdiv.s ft1, ft2, ft3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456
+
+# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE div a0, a1, a2
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 0.0 0.0 0.0 div a0, a1, a2
+# CHECK-NEXT: 1. 1 0.0 0.0 0.0 fdiv.s ft1, ft2, ft3
+# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
>From 9a5b7733fa93c4a18c800067a1209dc97edf7d1f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 30 Nov 2023 10:58:49 -0800
Subject: [PATCH 2/4] [RISCV] Rework IDiv and FDiv pipes on SiFive7
Set BufferSize=0 and remove Super pipes for these resources.
---
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 53ef9d1baf7b5..261c22ea35317 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in {
let BufferSize = 0 in {
def SiFive7PipeA : ProcResource<1>;
def SiFive7PipeB : ProcResource<1>;
+def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
+def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
def SiFive7PipeV : ProcResource<1>;
}
let BufferSize = 1 in {
-def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
-def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
def SiFive7VA : ProcResource<1> { let Super = SiFive7PipeV; } // Arithmetic sequencer
def SiFive7VL : ProcResource<1> { let Super = SiFive7PipeV; } // Load sequencer
def SiFive7VS : ProcResource<1> { let Super = SiFive7PipeV; } // Store sequencer
>From a79739da44f89cdb7d570d0d21a28491b7fbf1f8 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 1 Dec 2023 08:46:29 -0800
Subject: [PATCH 3/4] !fixup remove super
---
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 261c22ea35317..0f79b297e97c5 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -213,8 +213,8 @@ let SchedModel = SiFive7Model in {
let BufferSize = 0 in {
def SiFive7PipeA : ProcResource<1>;
def SiFive7PipeB : ProcResource<1>;
-def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
-def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
+def SiFive7IDiv : ProcResource<1>; // Int Division
+def SiFive7FDiv : ProcResource<1>; // FP Division/Sqrt
def SiFive7PipeV : ProcResource<1>;
}
>From 742fd85ba8a8a9abb86bd27ae45b1d102e51f092 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 4 Dec 2023 08:27:25 -0800
Subject: [PATCH 4/4] !fixup update test
---
.../tools/llvm-mca/RISCV/SiFive7/div-fdiv.s | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
index 544872c259c8e..5d274af333bc8 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
@@ -7,13 +7,13 @@ fdiv.s f1, f2, f3
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
-# CHECK-NEXT: Total Cycles: 94
+# CHECK-NEXT: Total Cycles: 67
# CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.02
-# CHECK-NEXT: IPC: 0.02
-# CHECK-NEXT: Block RThroughput: 93.0
+# CHECK-NEXT: uOps Per Cycle: 0.03
+# CHECK-NEXT: IPC: 0.03
+# CHECK-NEXT: Block RThroughput: 65.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -24,8 +24,8 @@ fdiv.s f1, f2, f3
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 66 66.00 div a0, a1, a2
-# CHECK-NEXT: 1 27 27.00 fdiv.s ft1, ft2, ft3
+# CHECK-NEXT: 1 66 65.00 div a0, a1, a2
+# CHECK-NEXT: 1 27 26.00 fdiv.s ft1, ft2, ft3
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
@@ -39,19 +39,19 @@ fdiv.s f1, f2, f3
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: 26.00 65.00 - 93.00 - - - -
+# CHECK-NEXT: 26.00 65.00 - 2.00 - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - 65.00 - 66.00 - - - - div a0, a1, a2
-# CHECK-NEXT: 26.00 - - 27.00 - - - - fdiv.s ft1, ft2, ft3
+# CHECK-NEXT: - 65.00 - 1.00 - - - - div a0, a1, a2
+# CHECK-NEXT: 26.00 - - 1.00 - - - - fdiv.s ft1, ft2, ft3
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456
# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE div a0, a1, a2
-# CHECK-NEXT: Truncated display due to cycle limit
+# CHECK-NEXT: [0,1] . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeeeeE fdiv.s ft1, ft2, ft3
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
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