[llvm] GlobalISel lane masks merging (PR #73337)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff 50c298fd174f1a98fd20374a65d1faecba5649e1 2d7e6f112cad920191031b8b9c64f84455f91d83 -- llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp llvm/lib/Target/AMDGPU/SILowerI1Copies.h llvm/include/llvm/CodeGen/MachineSSAUpdater.h llvm/lib/CodeGen/MachineSSAUpdater.cpp llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
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diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
index 42bb6aa9d0..449b9a20ac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
@@ -107,7 +107,6 @@ void DivergenceLoweringHelper::getCandidatesForLowering(
         Vreg1Phis.push_back(&MI);
     }
   }
-
 }
 
 void DivergenceLoweringHelper::collectIncomingValuesFromPhi(
@@ -138,7 +137,7 @@ getInsertAfterPtrs(MachineInstr *MI) {
 // bb.current
 // %CurReg = ...
 //
-// %DstReg - not defined 
+// %DstReg - not defined
 //
 // -> (wave32 example, new registers have sreg_32 reg class and S1 LLT)
 //
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 4472d6f2e4..f838ba7a71 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -412,7 +412,7 @@ FunctionPass *llvm::createSILowerI1CopiesPass() {
 }
 
 Register llvm::createLaneMaskReg(MachineRegisterInfo *MRI,
-                           Register *LaneMaskRegAttrs) {
+                                 Register *LaneMaskRegAttrs) {
   return MRI->cloneVirtualRegister(*LaneMaskRegAttrs);
 }
 

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https://github.com/llvm/llvm-project/pull/73337