[llvm] 0c568c2 - [SystemZ] Auto-generate vec-intrinsics tests
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 4 07:37:13 PST 2023
Author: Ulrich Weigand
Date: 2023-12-04T16:36:38+01:00
New Revision: 0c568c2535848d1596a612c15248f299ec8c42be
URL: https://github.com/llvm/llvm-project/commit/0c568c2535848d1596a612c15248f299ec8c42be
DIFF: https://github.com/llvm/llvm-project/commit/0c568c2535848d1596a612c15248f299ec8c42be.diff
LOG: [SystemZ] Auto-generate vec-intrinsics tests
Added:
Modified:
llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll
llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll
llvm/test/CodeGen/SystemZ/vec-intrinsics-03.ll
llvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll b/llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll
index 2de4f949cd37d..5338ccc9b4292 100644
--- a/llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector intrinsics.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
@@ -208,8 +209,9 @@ declare <2 x double> @llvm.s390.vfidb(<2 x double>, i32, i32)
; LCBB with the lowest M3 operand.
define i32 @test_lcbb1(ptr %ptr) {
; CHECK-LABEL: test_lcbb1:
-; CHECK: lcbb %r2, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcbb %r2, 0(%r2), 0
+; CHECK-NEXT: br %r14
%res = call i32 @llvm.s390.lcbb(ptr %ptr, i32 0)
ret i32 %res
}
@@ -217,8 +219,9 @@ define i32 @test_lcbb1(ptr %ptr) {
; LCBB with the highest M3 operand.
define i32 @test_lcbb2(ptr %ptr) {
; CHECK-LABEL: test_lcbb2:
-; CHECK: lcbb %r2, 0(%r2), 15
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcbb %r2, 0(%r2), 15
+; CHECK-NEXT: br %r14
%res = call i32 @llvm.s390.lcbb(ptr %ptr, i32 15)
ret i32 %res
}
@@ -226,8 +229,9 @@ define i32 @test_lcbb2(ptr %ptr) {
; LCBB with a displacement and index.
define i32 @test_lcbb3(ptr %base, i64 %index) {
; CHECK-LABEL: test_lcbb3:
-; CHECK: lcbb %r2, 4095({{%r2,%r3|%r3,%r2}}), 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lcbb %r2, 4095(%r2,%r3), 4
+; CHECK-NEXT: br %r14
%add = add i64 %index, 4095
%ptr = getelementptr i8, ptr %base, i64 %add
%res = call i32 @llvm.s390.lcbb(ptr %ptr, i32 4)
@@ -237,8 +241,10 @@ define i32 @test_lcbb3(ptr %base, i64 %index) {
; LCBB with an out-of-range displacement.
define i32 @test_lcbb4(ptr %base) {
; CHECK-LABEL: test_lcbb4:
-; CHECK: lcbb %r2, 0({{%r[1-5]}}), 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: lcbb %r2, 0(%r2), 5
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
%res = call i32 @llvm.s390.lcbb(ptr %ptr, i32 5)
ret i32 %res
@@ -247,8 +253,9 @@ define i32 @test_lcbb4(ptr %base) {
; VLBB with the lowest M3 operand.
define <16 x i8> @test_vlbb1(ptr %ptr) {
; CHECK-LABEL: test_vlbb1:
-; CHECK: vlbb %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbb %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vlbb(ptr %ptr, i32 0)
ret <16 x i8> %res
}
@@ -256,8 +263,9 @@ define <16 x i8> @test_vlbb1(ptr %ptr) {
; VLBB with the highest M3 operand.
define <16 x i8> @test_vlbb2(ptr %ptr) {
; CHECK-LABEL: test_vlbb2:
-; CHECK: vlbb %v24, 0(%r2), 15
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbb %v24, 0(%r2), 15
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vlbb(ptr %ptr, i32 15)
ret <16 x i8> %res
}
@@ -265,8 +273,9 @@ define <16 x i8> @test_vlbb2(ptr %ptr) {
; VLBB with a displacement and index.
define <16 x i8> @test_vlbb3(ptr %base, i64 %index) {
; CHECK-LABEL: test_vlbb3:
-; CHECK: vlbb %v24, 4095({{%r2,%r3|%r3,%r2}}), 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbb %v24, 4095(%r2,%r3), 4
+; CHECK-NEXT: br %r14
%add = add i64 %index, 4095
%ptr = getelementptr i8, ptr %base, i64 %add
%res = call <16 x i8> @llvm.s390.vlbb(ptr %ptr, i32 4)
@@ -276,8 +285,10 @@ define <16 x i8> @test_vlbb3(ptr %base, i64 %index) {
; VLBB with an out-of-range displacement.
define <16 x i8> @test_vlbb4(ptr %base) {
; CHECK-LABEL: test_vlbb4:
-; CHECK: vlbb %v24, 0({{%r[1-5]}}), 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlbb %v24, 0(%r2), 5
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
%res = call <16 x i8> @llvm.s390.vlbb(ptr %ptr, i32 5)
ret <16 x i8> %res
@@ -286,8 +297,9 @@ define <16 x i8> @test_vlbb4(ptr %base) {
; VLL with the lowest in-range displacement.
define <16 x i8> @test_vll1(ptr %ptr, i32 %length) {
; CHECK-LABEL: test_vll1:
-; CHECK: vll %v24, %r3, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vll %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vll(i32 %length, ptr %ptr)
ret <16 x i8> %res
}
@@ -295,8 +307,9 @@ define <16 x i8> @test_vll1(ptr %ptr, i32 %length) {
; VLL with the highest in-range displacement.
define <16 x i8> @test_vll2(ptr %base, i32 %length) {
; CHECK-LABEL: test_vll2:
-; CHECK: vll %v24, %r3, 4095(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vll %v24, %r3, 4095(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4095
%res = call <16 x i8> @llvm.s390.vll(i32 %length, ptr %ptr)
ret <16 x i8> %res
@@ -305,8 +318,10 @@ define <16 x i8> @test_vll2(ptr %base, i32 %length) {
; VLL with an out-of-range displacementa.
define <16 x i8> @test_vll3(ptr %base, i32 %length) {
; CHECK-LABEL: test_vll3:
-; CHECK: vll %v24, %r3, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vll %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
%res = call <16 x i8> @llvm.s390.vll(i32 %length, ptr %ptr)
ret <16 x i8> %res
@@ -315,8 +330,10 @@ define <16 x i8> @test_vll3(ptr %base, i32 %length) {
; Check that VLL doesn't allow an index.
define <16 x i8> @test_vll4(ptr %base, i64 %index, i32 %length) {
; CHECK-LABEL: test_vll4:
-; CHECK: vll %v24, %r4, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r2, %r3
+; CHECK-NEXT: vll %v24, %r4, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 %index
%res = call <16 x i8> @llvm.s390.vll(i32 %length, ptr %ptr)
ret <16 x i8> %res
@@ -325,8 +342,9 @@ define <16 x i8> @test_vll4(ptr %base, i64 %index, i32 %length) {
; VLL with length >= 15 should become VL.
define <16 x i8> @test_vll5(ptr %ptr) {
; CHECK-LABEL: test_vll5:
-; CHECK: vl %v24, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v24, 0(%r2), 3
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vll(i32 15, ptr %ptr)
ret <16 x i8> %res
}
@@ -334,8 +352,9 @@ define <16 x i8> @test_vll5(ptr %ptr) {
; VPDI taking element 0 from each half.
define <2 x i64> @test_vpdi1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vpdi1:
-; CHECK: vpdi %v24, %v24, %v26, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpdi %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 0)
ret <2 x i64> %res
}
@@ -343,8 +362,9 @@ define <2 x i64> @test_vpdi1(<2 x i64> %a, <2 x i64> %b) {
; VPDI taking element 1 from each half.
define <2 x i64> @test_vpdi2(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vpdi2:
-; CHECK: vpdi %v24, %v24, %v26, 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpdi %v24, %v24, %v26, 5
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 5)
ret <2 x i64> %res
}
@@ -352,8 +372,9 @@ define <2 x i64> @test_vpdi2(<2 x i64> %a, <2 x i64> %b) {
; VPERM.
define <16 x i8> @test_vperm(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vperm:
-; CHECK: vperm %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vperm %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vperm(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -362,8 +383,9 @@ define <16 x i8> @test_vperm(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VPKSH.
define <16 x i8> @test_vpksh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vpksh:
-; CHECK: vpksh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vpksh(<8 x i16> %a, <8 x i16> %b)
ret <16 x i8> %res
}
@@ -371,8 +393,9 @@ define <16 x i8> @test_vpksh(<8 x i16> %a, <8 x i16> %b) {
; VPKSF.
define <8 x i16> @test_vpksf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vpksf:
-; CHECK: vpksf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vpksf(<4 x i32> %a, <4 x i32> %b)
ret <8 x i16> %res
}
@@ -380,8 +403,9 @@ define <8 x i16> @test_vpksf(<4 x i32> %a, <4 x i32> %b) {
; VPKSG.
define <4 x i32> @test_vpksg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vpksg:
-; CHECK: vpksg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vpksg(<2 x i64> %a, <2 x i64> %b)
ret <4 x i32> %res
}
@@ -389,11 +413,12 @@ define <4 x i32> @test_vpksg(<2 x i64> %a, <2 x i64> %b) {
; VPKSHS with no processing of the result.
define <16 x i8> @test_vpkshs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vpkshs:
-; CHECK: vpkshs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpkshs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -404,10 +429,12 @@ define <16 x i8> @test_vpkshs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VPKSHS, storing to %ptr if all values were saturated.
define <16 x i8> @test_vpkshs_all_store(<8 x i16> %a, <8 x i16> %b, ptr %ptr) {
; CHECK-LABEL: test_vpkshs_all_store:
-; CHECK: vpkshs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpkshs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB20_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -425,11 +452,12 @@ exit:
; VPKSFS with no processing of the result.
define <8 x i16> @test_vpksfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vpksfs:
-; CHECK: vpksfs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksfs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -440,10 +468,12 @@ define <8 x i16> @test_vpksfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VPKSFS, storing to %ptr if any values were saturated.
define <8 x i16> @test_vpksfs_any_store(<4 x i32> %a, <4 x i32> %b, ptr %ptr) {
; CHECK-LABEL: test_vpksfs_any_store:
-; CHECK: vpksfs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksfs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB22_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -461,11 +491,12 @@ exit:
; VPKSGS with no processing of the result.
define <4 x i32> @test_vpksgs(<2 x i64> %a, <2 x i64> %b, ptr %ccptr) {
; CHECK-LABEL: test_vpksgs:
-; CHECK: vpksgs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksgs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -475,12 +506,14 @@ define <4 x i32> @test_vpksgs(<2 x i64> %a, <2 x i64> %b, ptr %ccptr) {
; VPKSGS, storing to %ptr if no elements were saturated
define <4 x i32> @test_vpksgs_none_store(<2 x i64> %a, <2 x i64> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vpksgs_none_store:
-; CHECK: vpksgs %v24, %v24, %v26
-; CHECK-NEXT: {{bnher|bner}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpksgs %v24, %v24, %v26
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB24_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -498,8 +531,9 @@ exit:
; VPKLSH.
define <16 x i8> @test_vpklsh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vpklsh:
-; CHECK: vpklsh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vpklsh(<8 x i16> %a, <8 x i16> %b)
ret <16 x i8> %res
}
@@ -507,8 +541,9 @@ define <16 x i8> @test_vpklsh(<8 x i16> %a, <8 x i16> %b) {
; VPKLSF.
define <8 x i16> @test_vpklsf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vpklsf:
-; CHECK: vpklsf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> %a, <4 x i32> %b)
ret <8 x i16> %res
}
@@ -516,8 +551,9 @@ define <8 x i16> @test_vpklsf(<4 x i32> %a, <4 x i32> %b) {
; VPKLSG.
define <4 x i32> @test_vpklsg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vpklsg:
-; CHECK: vpklsg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> %a, <2 x i64> %b)
ret <4 x i32> %res
}
@@ -525,11 +561,12 @@ define <4 x i32> @test_vpklsg(<2 x i64> %a, <2 x i64> %b) {
; VPKLSHS with no processing of the result.
define <16 x i8> @test_vpklshs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vpklshs:
-; CHECK: vpklshs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklshs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -539,12 +576,14 @@ define <16 x i8> @test_vpklshs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VPKLSHS, storing to %ptr if all values were saturated.
define <16 x i8> @test_vpklshs_all_store(<8 x i16> %a, <8 x i16> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vpklshs_all_store:
-; CHECK: vpklshs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklshs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB29_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -562,11 +601,12 @@ exit:
; VPKLSFS with no processing of the result.
define <8 x i16> @test_vpklsfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vpklsfs:
-; CHECK: vpklsfs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsfs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -576,12 +616,14 @@ define <8 x i16> @test_vpklsfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VPKLSFS, storing to %ptr if any values were saturated.
define <8 x i16> @test_vpklsfs_any_store(<4 x i32> %a, <4 x i32> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vpklsfs_any_store:
-; CHECK: vpklsfs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsfs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB31_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -599,11 +641,12 @@ exit:
; VPKLSGS with no processing of the result.
define <4 x i32> @test_vpklsgs(<2 x i64> %a, <2 x i64> %b, ptr %ccptr) {
; CHECK-LABEL: test_vpklsgs:
-; CHECK: vpklsgs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsgs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -613,12 +656,14 @@ define <4 x i32> @test_vpklsgs(<2 x i64> %a, <2 x i64> %b, ptr %ccptr) {
; VPKLSGS, storing to %ptr if no elements were saturated
define <4 x i32> @test_vpklsgs_none_store(<2 x i64> %a, <2 x i64> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vpklsgs_none_store:
-; CHECK: vpklsgs %v24, %v24, %v26
-; CHECK-NEXT: {{bnher|bner}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpklsgs %v24, %v24, %v26
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB33_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -636,8 +681,9 @@ exit:
; VSTL with the lowest in-range displacement.
define void @test_vstl1(<16 x i8> %vec, ptr %ptr, i32 %length) {
; CHECK-LABEL: test_vstl1:
-; CHECK: vstl %v24, %r3, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstl %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
}
@@ -645,8 +691,9 @@ define void @test_vstl1(<16 x i8> %vec, ptr %ptr, i32 %length) {
; VSTL with the highest in-range displacement.
define void @test_vstl2(<16 x i8> %vec, ptr %base, i32 %length) {
; CHECK-LABEL: test_vstl2:
-; CHECK: vstl %v24, %r3, 4095(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstl %v24, %r3, 4095(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4095
call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
@@ -655,8 +702,10 @@ define void @test_vstl2(<16 x i8> %vec, ptr %base, i32 %length) {
; VSTL with an out-of-range displacement.
define void @test_vstl3(<16 x i8> %vec, ptr %base, i32 %length) {
; CHECK-LABEL: test_vstl3:
-; CHECK: vstl %v24, %r3, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstl %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
@@ -665,8 +714,10 @@ define void @test_vstl3(<16 x i8> %vec, ptr %base, i32 %length) {
; Check that VSTL doesn't allow an index.
define void @test_vstl4(<16 x i8> %vec, ptr %base, i64 %index, i32 %length) {
; CHECK-LABEL: test_vstl4:
-; CHECK: vstl %v24, %r4, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r2, %r3
+; CHECK-NEXT: vstl %v24, %r4, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 %index
call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
@@ -675,8 +726,9 @@ define void @test_vstl4(<16 x i8> %vec, ptr %base, i64 %index, i32 %length) {
; VSTL with length >= 15 should become VST.
define void @test_vstl5(<16 x i8> %vec, ptr %ptr) {
; CHECK-LABEL: test_vstl5:
-; CHECK: vst %v24, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vst %v24, 0(%r2), 3
+; CHECK-NEXT: br %r14
call void @llvm.s390.vstl(<16 x i8> %vec, i32 15, ptr %ptr)
ret void
}
@@ -684,8 +736,9 @@ define void @test_vstl5(<16 x i8> %vec, ptr %ptr) {
; VUPHB.
define <8 x i16> @test_vuphb(<16 x i8> %a) {
; CHECK-LABEL: test_vuphb:
-; CHECK: vuphb %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuphb %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vuphb(<16 x i8> %a)
ret <8 x i16> %res
}
@@ -693,8 +746,9 @@ define <8 x i16> @test_vuphb(<16 x i8> %a) {
; VUPHH.
define <4 x i32> @test_vuphh(<8 x i16> %a) {
; CHECK-LABEL: test_vuphh:
-; CHECK: vuphh %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuphh %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vuphh(<8 x i16> %a)
ret <4 x i32> %res
}
@@ -702,8 +756,9 @@ define <4 x i32> @test_vuphh(<8 x i16> %a) {
; VUPHF.
define <2 x i64> @test_vuphf(<4 x i32> %a) {
; CHECK-LABEL: test_vuphf:
-; CHECK: vuphf %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuphf %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vuphf(<4 x i32> %a)
ret <2 x i64> %res
}
@@ -711,8 +766,9 @@ define <2 x i64> @test_vuphf(<4 x i32> %a) {
; VUPLHB.
define <8 x i16> @test_vuplhb(<16 x i8> %a) {
; CHECK-LABEL: test_vuplhb:
-; CHECK: vuplhb %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuplhb %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vuplhb(<16 x i8> %a)
ret <8 x i16> %res
}
@@ -720,8 +776,9 @@ define <8 x i16> @test_vuplhb(<16 x i8> %a) {
; VUPLHH.
define <4 x i32> @test_vuplhh(<8 x i16> %a) {
; CHECK-LABEL: test_vuplhh:
-; CHECK: vuplhh %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuplhh %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vuplhh(<8 x i16> %a)
ret <4 x i32> %res
}
@@ -729,8 +786,9 @@ define <4 x i32> @test_vuplhh(<8 x i16> %a) {
; VUPLHF.
define <2 x i64> @test_vuplhf(<4 x i32> %a) {
; CHECK-LABEL: test_vuplhf:
-; CHECK: vuplhf %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuplhf %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vuplhf(<4 x i32> %a)
ret <2 x i64> %res
}
@@ -738,8 +796,9 @@ define <2 x i64> @test_vuplhf(<4 x i32> %a) {
; VUPLB.
define <8 x i16> @test_vuplb(<16 x i8> %a) {
; CHECK-LABEL: test_vuplb:
-; CHECK: vuplb %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuplb %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vuplb(<16 x i8> %a)
ret <8 x i16> %res
}
@@ -747,8 +806,9 @@ define <8 x i16> @test_vuplb(<16 x i8> %a) {
; VUPLHW.
define <4 x i32> @test_vuplhw(<8 x i16> %a) {
; CHECK-LABEL: test_vuplhw:
-; CHECK: vuplhw %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuplhw %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vuplhw(<8 x i16> %a)
ret <4 x i32> %res
}
@@ -756,8 +816,9 @@ define <4 x i32> @test_vuplhw(<8 x i16> %a) {
; VUPLF.
define <2 x i64> @test_vuplf(<4 x i32> %a) {
; CHECK-LABEL: test_vuplf:
-; CHECK: vuplf %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vuplf %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vuplf(<4 x i32> %a)
ret <2 x i64> %res
}
@@ -765,8 +826,9 @@ define <2 x i64> @test_vuplf(<4 x i32> %a) {
; VUPLLB.
define <8 x i16> @test_vupllb(<16 x i8> %a) {
; CHECK-LABEL: test_vupllb:
-; CHECK: vupllb %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vupllb %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vupllb(<16 x i8> %a)
ret <8 x i16> %res
}
@@ -774,8 +836,9 @@ define <8 x i16> @test_vupllb(<16 x i8> %a) {
; VUPLLH.
define <4 x i32> @test_vupllh(<8 x i16> %a) {
; CHECK-LABEL: test_vupllh:
-; CHECK: vupllh %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vupllh %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vupllh(<8 x i16> %a)
ret <4 x i32> %res
}
@@ -783,8 +846,9 @@ define <4 x i32> @test_vupllh(<8 x i16> %a) {
; VUPLLF.
define <2 x i64> @test_vupllf(<4 x i32> %a) {
; CHECK-LABEL: test_vupllf:
-; CHECK: vupllf %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vupllf %v24, %v24
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vupllf(<4 x i32> %a)
ret <2 x i64> %res
}
@@ -792,8 +856,9 @@ define <2 x i64> @test_vupllf(<4 x i32> %a) {
; VACCB.
define <16 x i8> @test_vaccb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vaccb:
-; CHECK: vaccb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vaccb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vaccb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -801,8 +866,9 @@ define <16 x i8> @test_vaccb(<16 x i8> %a, <16 x i8> %b) {
; VACCH.
define <8 x i16> @test_vacch(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vacch:
-; CHECK: vacch %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vacch %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vacch(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -810,8 +876,9 @@ define <8 x i16> @test_vacch(<8 x i16> %a, <8 x i16> %b) {
; VACCF.
define <4 x i32> @test_vaccf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vaccf:
-; CHECK: vaccf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vaccf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vaccf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -819,8 +886,9 @@ define <4 x i32> @test_vaccf(<4 x i32> %a, <4 x i32> %b) {
; VACCG.
define <2 x i64> @test_vaccg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vaccg:
-; CHECK: vaccg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vaccg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vaccg(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %res
}
@@ -828,8 +896,9 @@ define <2 x i64> @test_vaccg(<2 x i64> %a, <2 x i64> %b) {
; VAQ.
define <16 x i8> @test_vaq(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vaq:
-; CHECK: vaq %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vaq %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vaq(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -837,8 +906,9 @@ define <16 x i8> @test_vaq(<16 x i8> %a, <16 x i8> %b) {
; VACQ.
define <16 x i8> @test_vacq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vacq:
-; CHECK: vacq %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vacq %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vacq(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -847,8 +917,9 @@ define <16 x i8> @test_vacq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VACCQ.
define <16 x i8> @test_vaccq(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vaccq:
-; CHECK: vaccq %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vaccq %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vaccq(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -856,8 +927,9 @@ define <16 x i8> @test_vaccq(<16 x i8> %a, <16 x i8> %b) {
; VACCCQ.
define <16 x i8> @test_vacccq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vacccq:
-; CHECK: vacccq %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vacccq %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vacccq(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -866,8 +938,9 @@ define <16 x i8> @test_vacccq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VAVGB.
define <16 x i8> @test_vavgb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vavgb:
-; CHECK: vavgb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavgb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vavgb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -875,8 +948,9 @@ define <16 x i8> @test_vavgb(<16 x i8> %a, <16 x i8> %b) {
; VAVGH.
define <8 x i16> @test_vavgh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vavgh:
-; CHECK: vavgh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavgh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vavgh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -884,8 +958,9 @@ define <8 x i16> @test_vavgh(<8 x i16> %a, <8 x i16> %b) {
; VAVGF.
define <4 x i32> @test_vavgf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vavgf:
-; CHECK: vavgf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavgf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vavgf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -893,8 +968,9 @@ define <4 x i32> @test_vavgf(<4 x i32> %a, <4 x i32> %b) {
; VAVGG.
define <2 x i64> @test_vavgg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vavgg:
-; CHECK: vavgg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavgg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vavgg(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %res
}
@@ -902,8 +978,9 @@ define <2 x i64> @test_vavgg(<2 x i64> %a, <2 x i64> %b) {
; VAVGLB.
define <16 x i8> @test_vavglb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vavglb:
-; CHECK: vavglb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavglb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vavglb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -911,8 +988,9 @@ define <16 x i8> @test_vavglb(<16 x i8> %a, <16 x i8> %b) {
; VAVGLH.
define <8 x i16> @test_vavglh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vavglh:
-; CHECK: vavglh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavglh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vavglh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -920,8 +998,9 @@ define <8 x i16> @test_vavglh(<8 x i16> %a, <8 x i16> %b) {
; VAVGLF.
define <4 x i32> @test_vavglf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vavglf:
-; CHECK: vavglf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavglf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vavglf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -929,8 +1008,9 @@ define <4 x i32> @test_vavglf(<4 x i32> %a, <4 x i32> %b) {
; VAVGLG.
define <2 x i64> @test_vavglg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vavglg:
-; CHECK: vavglg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vavglg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vavglg(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %res
}
@@ -938,8 +1018,9 @@ define <2 x i64> @test_vavglg(<2 x i64> %a, <2 x i64> %b) {
; VCKSM.
define <4 x i32> @test_vcksm(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vcksm:
-; CHECK: vcksm %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcksm %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vcksm(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -947,8 +1028,9 @@ define <4 x i32> @test_vcksm(<4 x i32> %a, <4 x i32> %b) {
; VGFMB.
define <8 x i16> @test_vgfmb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vgfmb:
-; CHECK: vgfmb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vgfmb(<16 x i8> %a, <16 x i8> %b)
ret <8 x i16> %res
}
@@ -956,8 +1038,9 @@ define <8 x i16> @test_vgfmb(<16 x i8> %a, <16 x i8> %b) {
; VGFMH.
define <4 x i32> @test_vgfmh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vgfmh:
-; CHECK: vgfmh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vgfmh(<8 x i16> %a, <8 x i16> %b)
ret <4 x i32> %res
}
@@ -965,8 +1048,9 @@ define <4 x i32> @test_vgfmh(<8 x i16> %a, <8 x i16> %b) {
; VGFMF.
define <2 x i64> @test_vgfmf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vgfmf:
-; CHECK: vgfmf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vgfmf(<4 x i32> %a, <4 x i32> %b)
ret <2 x i64> %res
}
@@ -974,8 +1058,9 @@ define <2 x i64> @test_vgfmf(<4 x i32> %a, <4 x i32> %b) {
; VGFMG.
define <16 x i8> @test_vgfmg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vgfmg:
-; CHECK: vgfmg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vgfmg(<2 x i64> %a, <2 x i64> %b)
ret <16 x i8> %res
}
@@ -983,8 +1068,9 @@ define <16 x i8> @test_vgfmg(<2 x i64> %a, <2 x i64> %b) {
; VGFMAB.
define <8 x i16> @test_vgfmab(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vgfmab:
-; CHECK: vgfmab %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmab %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vgfmab(<16 x i8> %a, <16 x i8> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -993,8 +1079,9 @@ define <8 x i16> @test_vgfmab(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; VGFMAH.
define <4 x i32> @test_vgfmah(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vgfmah:
-; CHECK: vgfmah %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmah %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vgfmah(<8 x i16> %a, <8 x i16> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1003,8 +1090,9 @@ define <4 x i32> @test_vgfmah(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; VGFMAF.
define <2 x i64> @test_vgfmaf(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; CHECK-LABEL: test_vgfmaf:
-; CHECK: vgfmaf %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmaf %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vgfmaf(<4 x i32> %a, <4 x i32> %b,
<2 x i64> %c)
ret <2 x i64> %res
@@ -1013,8 +1101,9 @@ define <2 x i64> @test_vgfmaf(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; VGFMAG.
define <16 x i8> @test_vgfmag(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vgfmag:
-; CHECK: vgfmag %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgfmag %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vgfmag(<2 x i64> %a, <2 x i64> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -1023,8 +1112,9 @@ define <16 x i8> @test_vgfmag(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
; VMAHB.
define <16 x i8> @test_vmahb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vmahb:
-; CHECK: vmahb %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmahb %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vmahb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -1033,8 +1123,9 @@ define <16 x i8> @test_vmahb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VMAHH.
define <8 x i16> @test_vmahh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vmahh:
-; CHECK: vmahh %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmahh %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmahh(<8 x i16> %a, <8 x i16> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -1043,8 +1134,9 @@ define <8 x i16> @test_vmahh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; VMAHF.
define <4 x i32> @test_vmahf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vmahf:
-; CHECK: vmahf %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmahf %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmahf(<4 x i32> %a, <4 x i32> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1053,8 +1145,9 @@ define <4 x i32> @test_vmahf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; VMALHB.
define <16 x i8> @test_vmalhb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vmalhb:
-; CHECK: vmalhb %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmalhb %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vmalhb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -1063,8 +1156,9 @@ define <16 x i8> @test_vmalhb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VMALHH.
define <8 x i16> @test_vmalhh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vmalhh:
-; CHECK: vmalhh %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmalhh %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmalhh(<8 x i16> %a, <8 x i16> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -1073,8 +1167,9 @@ define <8 x i16> @test_vmalhh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; VMALHF.
define <4 x i32> @test_vmalhf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vmalhf:
-; CHECK: vmalhf %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmalhf %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmalhf(<4 x i32> %a, <4 x i32> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1083,8 +1178,9 @@ define <4 x i32> @test_vmalhf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; VMAEB.
define <8 x i16> @test_vmaeb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vmaeb:
-; CHECK: vmaeb %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaeb %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmaeb(<16 x i8> %a, <16 x i8> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -1093,8 +1189,9 @@ define <8 x i16> @test_vmaeb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; VMAEH.
define <4 x i32> @test_vmaeh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vmaeh:
-; CHECK: vmaeh %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaeh %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmaeh(<8 x i16> %a, <8 x i16> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1103,8 +1200,9 @@ define <4 x i32> @test_vmaeh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; VMAEF.
define <2 x i64> @test_vmaef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; CHECK-LABEL: test_vmaef:
-; CHECK: vmaef %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaef %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmaef(<4 x i32> %a, <4 x i32> %b,
<2 x i64> %c)
ret <2 x i64> %res
@@ -1113,8 +1211,9 @@ define <2 x i64> @test_vmaef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; VMALEB.
define <8 x i16> @test_vmaleb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vmaleb:
-; CHECK: vmaleb %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaleb %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmaleb(<16 x i8> %a, <16 x i8> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -1123,8 +1222,9 @@ define <8 x i16> @test_vmaleb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; VMALEH.
define <4 x i32> @test_vmaleh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vmaleh:
-; CHECK: vmaleh %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaleh %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmaleh(<8 x i16> %a, <8 x i16> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1133,8 +1233,9 @@ define <4 x i32> @test_vmaleh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; VMALEF.
define <2 x i64> @test_vmalef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; CHECK-LABEL: test_vmalef:
-; CHECK: vmalef %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmalef %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmalef(<4 x i32> %a, <4 x i32> %b,
<2 x i64> %c)
ret <2 x i64> %res
@@ -1143,8 +1244,9 @@ define <2 x i64> @test_vmalef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; VMAOB.
define <8 x i16> @test_vmaob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vmaob:
-; CHECK: vmaob %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaob %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmaob(<16 x i8> %a, <16 x i8> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -1153,8 +1255,9 @@ define <8 x i16> @test_vmaob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; VMAOH.
define <4 x i32> @test_vmaoh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vmaoh:
-; CHECK: vmaoh %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaoh %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmaoh(<8 x i16> %a, <8 x i16> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1163,8 +1266,9 @@ define <4 x i32> @test_vmaoh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; VMAOF.
define <2 x i64> @test_vmaof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; CHECK-LABEL: test_vmaof:
-; CHECK: vmaof %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaof %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmaof(<4 x i32> %a, <4 x i32> %b,
<2 x i64> %c)
ret <2 x i64> %res
@@ -1173,8 +1277,9 @@ define <2 x i64> @test_vmaof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; VMALOB.
define <8 x i16> @test_vmalob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vmalob:
-; CHECK: vmalob %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmalob %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmalob(<16 x i8> %a, <16 x i8> %b,
<8 x i16> %c)
ret <8 x i16> %res
@@ -1183,8 +1288,9 @@ define <8 x i16> @test_vmalob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) {
; VMALOH.
define <4 x i32> @test_vmaloh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vmaloh:
-; CHECK: vmaloh %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaloh %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmaloh(<8 x i16> %a, <8 x i16> %b,
<4 x i32> %c)
ret <4 x i32> %res
@@ -1193,8 +1299,9 @@ define <4 x i32> @test_vmaloh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) {
; VMALOF.
define <2 x i64> @test_vmalof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; CHECK-LABEL: test_vmalof:
-; CHECK: vmalof %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmalof %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmalof(<4 x i32> %a, <4 x i32> %b,
<2 x i64> %c)
ret <2 x i64> %res
@@ -1203,8 +1310,9 @@ define <2 x i64> @test_vmalof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) {
; VMHB.
define <16 x i8> @test_vmhb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vmhb:
-; CHECK: vmhb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmhb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vmhb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1212,8 +1320,9 @@ define <16 x i8> @test_vmhb(<16 x i8> %a, <16 x i8> %b) {
; VMHH.
define <8 x i16> @test_vmhh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vmhh:
-; CHECK: vmhh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmhh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmhh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -1221,8 +1330,9 @@ define <8 x i16> @test_vmhh(<8 x i16> %a, <8 x i16> %b) {
; VMHF.
define <4 x i32> @test_vmhf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vmhf:
-; CHECK: vmhf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmhf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmhf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -1230,8 +1340,9 @@ define <4 x i32> @test_vmhf(<4 x i32> %a, <4 x i32> %b) {
; VMLHB.
define <16 x i8> @test_vmlhb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vmlhb:
-; CHECK: vmlhb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmlhb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vmlhb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1239,8 +1350,9 @@ define <16 x i8> @test_vmlhb(<16 x i8> %a, <16 x i8> %b) {
; VMLHH.
define <8 x i16> @test_vmlhh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vmlhh:
-; CHECK: vmlhh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmlhh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmlhh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -1248,8 +1360,9 @@ define <8 x i16> @test_vmlhh(<8 x i16> %a, <8 x i16> %b) {
; VMLHF.
define <4 x i32> @test_vmlhf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vmlhf:
-; CHECK: vmlhf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmlhf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmlhf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -1257,8 +1370,9 @@ define <4 x i32> @test_vmlhf(<4 x i32> %a, <4 x i32> %b) {
; VMEB.
define <8 x i16> @test_vmeb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vmeb:
-; CHECK: vmeb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmeb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmeb(<16 x i8> %a, <16 x i8> %b)
ret <8 x i16> %res
}
@@ -1266,8 +1380,9 @@ define <8 x i16> @test_vmeb(<16 x i8> %a, <16 x i8> %b) {
; VMEH.
define <4 x i32> @test_vmeh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vmeh:
-; CHECK: vmeh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmeh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmeh(<8 x i16> %a, <8 x i16> %b)
ret <4 x i32> %res
}
@@ -1275,8 +1390,9 @@ define <4 x i32> @test_vmeh(<8 x i16> %a, <8 x i16> %b) {
; VMEF.
define <2 x i64> @test_vmef(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vmef:
-; CHECK: vmef %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmef %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmef(<4 x i32> %a, <4 x i32> %b)
ret <2 x i64> %res
}
@@ -1284,8 +1400,9 @@ define <2 x i64> @test_vmef(<4 x i32> %a, <4 x i32> %b) {
; VMLEB.
define <8 x i16> @test_vmleb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vmleb:
-; CHECK: vmleb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmleb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmleb(<16 x i8> %a, <16 x i8> %b)
ret <8 x i16> %res
}
@@ -1293,8 +1410,9 @@ define <8 x i16> @test_vmleb(<16 x i8> %a, <16 x i8> %b) {
; VMLEH.
define <4 x i32> @test_vmleh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vmleh:
-; CHECK: vmleh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmleh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmleh(<8 x i16> %a, <8 x i16> %b)
ret <4 x i32> %res
}
@@ -1302,8 +1420,9 @@ define <4 x i32> @test_vmleh(<8 x i16> %a, <8 x i16> %b) {
; VMLEF.
define <2 x i64> @test_vmlef(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vmlef:
-; CHECK: vmlef %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmlef %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmlef(<4 x i32> %a, <4 x i32> %b)
ret <2 x i64> %res
}
@@ -1311,8 +1430,9 @@ define <2 x i64> @test_vmlef(<4 x i32> %a, <4 x i32> %b) {
; VMOB.
define <8 x i16> @test_vmob(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vmob:
-; CHECK: vmob %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmob %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmob(<16 x i8> %a, <16 x i8> %b)
ret <8 x i16> %res
}
@@ -1320,8 +1440,9 @@ define <8 x i16> @test_vmob(<16 x i8> %a, <16 x i8> %b) {
; VMOH.
define <4 x i32> @test_vmoh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vmoh:
-; CHECK: vmoh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmoh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmoh(<8 x i16> %a, <8 x i16> %b)
ret <4 x i32> %res
}
@@ -1329,8 +1450,9 @@ define <4 x i32> @test_vmoh(<8 x i16> %a, <8 x i16> %b) {
; VMOF.
define <2 x i64> @test_vmof(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vmof:
-; CHECK: vmof %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmof %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmof(<4 x i32> %a, <4 x i32> %b)
ret <2 x i64> %res
}
@@ -1338,8 +1460,9 @@ define <2 x i64> @test_vmof(<4 x i32> %a, <4 x i32> %b) {
; VMLOB.
define <8 x i16> @test_vmlob(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vmlob:
-; CHECK: vmlob %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmlob %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vmlob(<16 x i8> %a, <16 x i8> %b)
ret <8 x i16> %res
}
@@ -1347,8 +1470,9 @@ define <8 x i16> @test_vmlob(<16 x i8> %a, <16 x i8> %b) {
; VMLOH.
define <4 x i32> @test_vmloh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vmloh:
-; CHECK: vmloh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmloh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vmloh(<8 x i16> %a, <8 x i16> %b)
ret <4 x i32> %res
}
@@ -1356,8 +1480,9 @@ define <4 x i32> @test_vmloh(<8 x i16> %a, <8 x i16> %b) {
; VMLOF.
define <2 x i64> @test_vmlof(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vmlof:
-; CHECK: vmlof %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmlof %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vmlof(<4 x i32> %a, <4 x i32> %b)
ret <2 x i64> %res
}
@@ -1365,8 +1490,9 @@ define <2 x i64> @test_vmlof(<4 x i32> %a, <4 x i32> %b) {
; VERLLVB.
define <16 x i8> @test_verllvb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_verllvb:
-; CHECK: verllvb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllvb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verllvb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1374,8 +1500,9 @@ define <16 x i8> @test_verllvb(<16 x i8> %a, <16 x i8> %b) {
; VERLLVH.
define <8 x i16> @test_verllvh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_verllvh:
-; CHECK: verllvh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllvh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.verllvh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -1383,8 +1510,9 @@ define <8 x i16> @test_verllvh(<8 x i16> %a, <8 x i16> %b) {
; VERLLVF.
define <4 x i32> @test_verllvf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_verllvf:
-; CHECK: verllvf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllvf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.verllvf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -1392,8 +1520,9 @@ define <4 x i32> @test_verllvf(<4 x i32> %a, <4 x i32> %b) {
; VERLLVG.
define <2 x i64> @test_verllvg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_verllvg:
-; CHECK: verllvg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllvg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.verllvg(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %res
}
@@ -1401,8 +1530,9 @@ define <2 x i64> @test_verllvg(<2 x i64> %a, <2 x i64> %b) {
; VERLLB.
define <16 x i8> @test_verllb(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_verllb:
-; CHECK: verllb %v24, %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllb %v24, %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 %b)
ret <16 x i8> %res
}
@@ -1410,8 +1540,9 @@ define <16 x i8> @test_verllb(<16 x i8> %a, i32 %b) {
; VERLLH.
define <8 x i16> @test_verllh(<8 x i16> %a, i32 %b) {
; CHECK-LABEL: test_verllh:
-; CHECK: verllh %v24, %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllh %v24, %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.verllh(<8 x i16> %a, i32 %b)
ret <8 x i16> %res
}
@@ -1419,8 +1550,9 @@ define <8 x i16> @test_verllh(<8 x i16> %a, i32 %b) {
; VERLLF.
define <4 x i32> @test_verllf(<4 x i32> %a, i32 %b) {
; CHECK-LABEL: test_verllf:
-; CHECK: verllf %v24, %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllf %v24, %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.verllf(<4 x i32> %a, i32 %b)
ret <4 x i32> %res
}
@@ -1428,8 +1560,9 @@ define <4 x i32> @test_verllf(<4 x i32> %a, i32 %b) {
; VERLLG.
define <2 x i64> @test_verllg(<2 x i64> %a, i32 %b) {
; CHECK-LABEL: test_verllg:
-; CHECK: verllg %v24, %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllg %v24, %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.verllg(<2 x i64> %a, i32 %b)
ret <2 x i64> %res
}
@@ -1437,8 +1570,9 @@ define <2 x i64> @test_verllg(<2 x i64> %a, i32 %b) {
; VERLLB with the smallest count.
define <16 x i8> @test_verllb_1(<16 x i8> %a) {
; CHECK-LABEL: test_verllb_1:
-; CHECK: verllb %v24, %v24, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllb %v24, %v24, 1
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 1)
ret <16 x i8> %res
}
@@ -1446,8 +1580,9 @@ define <16 x i8> @test_verllb_1(<16 x i8> %a) {
; VERLLB with the largest count.
define <16 x i8> @test_verllb_4095(<16 x i8> %a) {
; CHECK-LABEL: test_verllb_4095:
-; CHECK: verllb %v24, %v24, 4095
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verllb %v24, %v24, 4095
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4095)
ret <16 x i8> %res
}
@@ -1455,9 +1590,10 @@ define <16 x i8> @test_verllb_4095(<16 x i8> %a) {
; VERLLB with the largest count + 1.
define <16 x i8> @test_verllb_4096(<16 x i8> %a) {
; CHECK-LABEL: test_verllb_4096:
-; CHECK: lhi [[REG:%r[1-5]]], 4096
-; CHECK: verllb %v24, %v24, 0([[REG]])
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lhi %r1, 4096
+; CHECK-NEXT: verllb %v24, %v24, 0(%r1)
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4096)
ret <16 x i8> %res
}
@@ -1465,8 +1601,9 @@ define <16 x i8> @test_verllb_4096(<16 x i8> %a) {
; VERIMB.
define <16 x i8> @test_verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_verimb:
-; CHECK: verimb %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verimb %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)
ret <16 x i8> %res
}
@@ -1474,8 +1611,9 @@ define <16 x i8> @test_verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VERIMH.
define <8 x i16> @test_verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; CHECK-LABEL: test_verimh:
-; CHECK: verimh %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verimh %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, i32 1)
ret <8 x i16> %res
}
@@ -1483,8 +1621,9 @@ define <8 x i16> @test_verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; VERIMF.
define <4 x i32> @test_verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: test_verimf:
-; CHECK: verimf %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verimf %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i32 1)
ret <4 x i32> %res
}
@@ -1492,8 +1631,9 @@ define <4 x i32> @test_verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; VERIMG.
define <2 x i64> @test_verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
; CHECK-LABEL: test_verimg:
-; CHECK: verimg %v24, %v26, %v28, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verimg %v24, %v26, %v28, 1
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 1)
ret <2 x i64> %res
}
@@ -1501,8 +1641,9 @@ define <2 x i64> @test_verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
; VERIMB with a
diff erent mask.
define <16 x i8> @test_verimb_254(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_verimb_254:
-; CHECK: verimb %v24, %v26, %v28, 254
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: verimb %v24, %v26, %v28, 254
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 254)
ret <16 x i8> %res
}
@@ -1510,8 +1651,9 @@ define <16 x i8> @test_verimb_254(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSL.
define <16 x i8> @test_vsl(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsl:
-; CHECK: vsl %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsl %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsl(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1519,8 +1661,9 @@ define <16 x i8> @test_vsl(<16 x i8> %a, <16 x i8> %b) {
; VSLB.
define <16 x i8> @test_vslb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vslb:
-; CHECK: vslb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vslb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vslb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1528,8 +1671,9 @@ define <16 x i8> @test_vslb(<16 x i8> %a, <16 x i8> %b) {
; VSRA.
define <16 x i8> @test_vsra(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsra:
-; CHECK: vsra %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsra %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsra(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1537,8 +1681,9 @@ define <16 x i8> @test_vsra(<16 x i8> %a, <16 x i8> %b) {
; VSRAB.
define <16 x i8> @test_vsrab(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsrab:
-; CHECK: vsrab %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsrab %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsrab(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1546,8 +1691,9 @@ define <16 x i8> @test_vsrab(<16 x i8> %a, <16 x i8> %b) {
; VSRL.
define <16 x i8> @test_vsrl(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsrl:
-; CHECK: vsrl %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsrl %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsrl(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1555,8 +1701,9 @@ define <16 x i8> @test_vsrl(<16 x i8> %a, <16 x i8> %b) {
; VSRLB.
define <16 x i8> @test_vsrlb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsrlb:
-; CHECK: vsrlb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsrlb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsrlb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1564,8 +1711,9 @@ define <16 x i8> @test_vsrlb(<16 x i8> %a, <16 x i8> %b) {
; VSLDB with the minimum useful value.
define <16 x i8> @test_vsldb_1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsldb_1:
-; CHECK: vsldb %v24, %v24, %v26, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsldb %v24, %v24, %v26, 1
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 1)
ret <16 x i8> %res
}
@@ -1573,8 +1721,9 @@ define <16 x i8> @test_vsldb_1(<16 x i8> %a, <16 x i8> %b) {
; VSLDB with the maximum value.
define <16 x i8> @test_vsldb_15(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsldb_15:
-; CHECK: vsldb %v24, %v24, %v26, 15
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsldb %v24, %v24, %v26, 15
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 15)
ret <16 x i8> %res
}
@@ -1582,8 +1731,9 @@ define <16 x i8> @test_vsldb_15(<16 x i8> %a, <16 x i8> %b) {
; VSCBIB.
define <16 x i8> @test_vscbib(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vscbib:
-; CHECK: vscbib %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vscbib %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vscbib(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1591,8 +1741,9 @@ define <16 x i8> @test_vscbib(<16 x i8> %a, <16 x i8> %b) {
; VSCBIH.
define <8 x i16> @test_vscbih(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vscbih:
-; CHECK: vscbih %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vscbih %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vscbih(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -1600,8 +1751,9 @@ define <8 x i16> @test_vscbih(<8 x i16> %a, <8 x i16> %b) {
; VSCBIF.
define <4 x i32> @test_vscbif(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vscbif:
-; CHECK: vscbif %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vscbif %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vscbif(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -1609,8 +1761,9 @@ define <4 x i32> @test_vscbif(<4 x i32> %a, <4 x i32> %b) {
; VSCBIG.
define <2 x i64> @test_vscbig(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vscbig:
-; CHECK: vscbig %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vscbig %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vscbig(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %res
}
@@ -1618,8 +1771,9 @@ define <2 x i64> @test_vscbig(<2 x i64> %a, <2 x i64> %b) {
; VSQ.
define <16 x i8> @test_vsq(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsq:
-; CHECK: vsq %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsq %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsq(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1627,8 +1781,9 @@ define <16 x i8> @test_vsq(<16 x i8> %a, <16 x i8> %b) {
; VSBIQ.
define <16 x i8> @test_vsbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vsbiq:
-; CHECK: vsbiq %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsbiq %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsbiq(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -1637,8 +1792,9 @@ define <16 x i8> @test_vsbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSCBIQ.
define <16 x i8> @test_vscbiq(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vscbiq:
-; CHECK: vscbiq %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vscbiq %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vscbiq(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -1646,8 +1802,9 @@ define <16 x i8> @test_vscbiq(<16 x i8> %a, <16 x i8> %b) {
; VSBCBIQ.
define <16 x i8> @test_vsbcbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vsbcbiq:
-; CHECK: vsbcbiq %v24, %v24, %v26, %v28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsbcbiq %v24, %v24, %v26, %v28
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsbcbiq(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
ret <16 x i8> %res
@@ -1656,8 +1813,9 @@ define <16 x i8> @test_vsbcbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSUMB.
define <4 x i32> @test_vsumb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsumb:
-; CHECK: vsumb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsumb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vsumb(<16 x i8> %a, <16 x i8> %b)
ret <4 x i32> %res
}
@@ -1665,8 +1823,9 @@ define <4 x i32> @test_vsumb(<16 x i8> %a, <16 x i8> %b) {
; VSUMH.
define <4 x i32> @test_vsumh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vsumh:
-; CHECK: vsumh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsumh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vsumh(<8 x i16> %a, <8 x i16> %b)
ret <4 x i32> %res
}
@@ -1674,8 +1833,9 @@ define <4 x i32> @test_vsumh(<8 x i16> %a, <8 x i16> %b) {
; VSUMGH.
define <2 x i64> @test_vsumgh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vsumgh:
-; CHECK: vsumgh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsumgh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vsumgh(<8 x i16> %a, <8 x i16> %b)
ret <2 x i64> %res
}
@@ -1683,8 +1843,9 @@ define <2 x i64> @test_vsumgh(<8 x i16> %a, <8 x i16> %b) {
; VSUMGF.
define <2 x i64> @test_vsumgf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vsumgf:
-; CHECK: vsumgf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsumgf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vsumgf(<4 x i32> %a, <4 x i32> %b)
ret <2 x i64> %res
}
@@ -1692,8 +1853,9 @@ define <2 x i64> @test_vsumgf(<4 x i32> %a, <4 x i32> %b) {
; VSUMQF.
define <16 x i8> @test_vsumqf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vsumqf:
-; CHECK: vsumqf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsumqf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsumqf(<4 x i32> %a, <4 x i32> %b)
ret <16 x i8> %res
}
@@ -1701,8 +1863,9 @@ define <16 x i8> @test_vsumqf(<4 x i32> %a, <4 x i32> %b) {
; VSUMQG.
define <16 x i8> @test_vsumqg(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vsumqg:
-; CHECK: vsumqg %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsumqg %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsumqg(<2 x i64> %a, <2 x i64> %b)
ret <16 x i8> %res
}
@@ -1710,10 +1873,11 @@ define <16 x i8> @test_vsumqg(<2 x i64> %a, <2 x i64> %b) {
; VTM with no processing of the result.
define i32 @test_vtm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vtm:
-; CHECK: vtm %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vtm %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b)
ret i32 %res
}
@@ -1721,11 +1885,12 @@ define i32 @test_vtm(<16 x i8> %a, <16 x i8> %b) {
; VTM, storing to %ptr if all bits are set.
define void @test_vtm_all_store(<16 x i8> %a, <16 x i8> %b, ptr %ptr) {
; CHECK-LABEL: test_vtm_all_store:
-; CHECK-NOT: %r
-; CHECK: vtm %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vtm %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB151_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b)
%cmp = icmp sge i32 %res, 3
br i1 %cmp, label %store, label %exit
@@ -1741,10 +1906,11 @@ exit:
; VCEQBS with no processing of the result.
define i32 @test_vceqbs(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vceqbs:
-; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
ret i32 %res
@@ -1753,10 +1919,11 @@ define i32 @test_vceqbs(<16 x i8> %a, <16 x i8> %b) {
; VCEQBS, returning 1 if any elements are equal (CC != 3).
define i32 @test_vceqbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vceqbs_any_bool:
-; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochile %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochile %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
%cmp = icmp ne i32 %res, 3
@@ -1767,11 +1934,12 @@ define i32 @test_vceqbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; VCEQBS, storing to %ptr if any elements are equal.
define <16 x i8> @test_vceqbs_any_store(<16 x i8> %a, <16 x i8> %b, ptr %ptr) {
; CHECK-LABEL: test_vceqbs_any_store:
-; CHECK-NOT: %r
-; CHECK: vceqbs %v24, %v24, %v26
-; CHECK-NEXT: {{bor|bnler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqbs %v24, %v24, %v26
+; CHECK-NEXT: bor %r14
+; CHECK-NEXT: .LBB154_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -1789,10 +1957,11 @@ exit:
; VCEQHS with no processing of the result.
define i32 @test_vceqhs(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vceqhs:
-; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqhs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
ret i32 %res
@@ -1801,10 +1970,11 @@ define i32 @test_vceqhs(<8 x i16> %a, <8 x i16> %b) {
; VCEQHS, returning 1 if not all elements are equal.
define i32 @test_vceqhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vceqhs_notall_bool:
-; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochinhe %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqhs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochinhe %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
%cmp = icmp sge i32 %res, 1
@@ -1814,13 +1984,14 @@ define i32 @test_vceqhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; VCEQHS, storing to %ptr if not all elements are equal.
define <8 x i16> @test_vceqhs_notall_store(<8 x i16> %a, <8 x i16> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vceqhs_notall_store:
-; CHECK-NOT: %r
-; CHECK: vceqhs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqhs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB157_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -1838,10 +2009,11 @@ exit:
; VCEQFS with no processing of the result.
define i32 @test_vceqfs(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vceqfs:
-; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqfs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
ret i32 %res
@@ -1850,10 +2022,11 @@ define i32 @test_vceqfs(<4 x i32> %a, <4 x i32> %b) {
; VCEQFS, returning 1 if no elements are equal.
define i32 @test_vceqfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vceqfs_none_bool:
-; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochio %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqfs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochio %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
%cmp = icmp eq i32 %res, 3
@@ -1863,13 +2036,14 @@ define i32 @test_vceqfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; VCEQFS, storing to %ptr if no elements are equal.
define <4 x i32> @test_vceqfs_none_store(<4 x i32> %a, <4 x i32> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vceqfs_none_store:
-; CHECK-NOT: %r
-; CHECK: vceqfs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqfs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB160_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -1887,10 +2061,11 @@ exit:
; VCEQGS with no processing of the result.
define i32 @test_vceqgs(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vceqgs:
-; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqgs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
ret i32 %res
@@ -1899,10 +2074,11 @@ define i32 @test_vceqgs(<2 x i64> %a, <2 x i64> %b) {
; VCEQGS returning 1 if all elements are equal (CC == 0).
define i32 @test_vceqgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vceqgs_all_bool:
-; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochie %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqgs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochie %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
%cmp = icmp ult i32 %res, 1
@@ -1913,11 +2089,12 @@ define i32 @test_vceqgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; VCEQGS, storing to %ptr if all elements are equal.
define <2 x i64> @test_vceqgs_all_store(<2 x i64> %a, <2 x i64> %b, ptr %ptr) {
; CHECK-LABEL: test_vceqgs_all_store:
-; CHECK-NOT: %r
-; CHECK: vceqgs %v24, %v24, %v26
-; CHECK-NEXT: {{bnher|bner}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vceqgs %v24, %v24, %v26
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB163_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 0
%cc = extractvalue {<2 x i64>, i32} %call, 1
@@ -1935,10 +2112,11 @@ exit:
; VCHBS with no processing of the result.
define i32 @test_vchbs(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vchbs:
-; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
ret i32 %res
@@ -1947,10 +2125,11 @@ define i32 @test_vchbs(<16 x i8> %a, <16 x i8> %b) {
; VCHBS, returning 1 if any elements are higher (CC != 3).
define i32 @test_vchbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vchbs_any_bool:
-; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochile %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochile %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
%cmp = icmp ne i32 %res, 3
@@ -1961,11 +2140,12 @@ define i32 @test_vchbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; VCHBS, storing to %ptr if any elements are higher.
define <16 x i8> @test_vchbs_any_store(<16 x i8> %a, <16 x i8> %b, ptr %ptr) {
; CHECK-LABEL: test_vchbs_any_store:
-; CHECK-NOT: %r
-; CHECK: vchbs %v24, %v24, %v26
-; CHECK-NEXT: {{bor|bnler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchbs %v24, %v24, %v26
+; CHECK-NEXT: bor %r14
+; CHECK-NEXT: .LBB166_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -1983,10 +2163,11 @@ exit:
; VCHHS with no processing of the result.
define i32 @test_vchhs(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vchhs:
-; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchhs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
ret i32 %res
@@ -1995,10 +2176,11 @@ define i32 @test_vchhs(<8 x i16> %a, <8 x i16> %b) {
; VCHHS, returning 1 if not all elements are higher.
define i32 @test_vchhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vchhs_notall_bool:
-; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochinhe %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchhs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochinhe %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
%cmp = icmp sge i32 %res, 1
@@ -2008,13 +2190,14 @@ define i32 @test_vchhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; VCHHS, storing to %ptr if not all elements are higher.
define <8 x i16> @test_vchhs_notall_store(<8 x i16> %a, <8 x i16> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vchhs_notall_store:
-; CHECK-NOT: %r
-; CHECK: vchhs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchhs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB169_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2032,10 +2215,11 @@ exit:
; VCHFS with no processing of the result.
define i32 @test_vchfs(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vchfs:
-; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchfs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
ret i32 %res
@@ -2044,10 +2228,11 @@ define i32 @test_vchfs(<4 x i32> %a, <4 x i32> %b) {
; VCHFS, returning 1 if no elements are higher.
define i32 @test_vchfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vchfs_none_bool:
-; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochio %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchfs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochio %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
%cmp = icmp eq i32 %res, 3
@@ -2058,11 +2243,12 @@ define i32 @test_vchfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; VCHFS, storing to %ptr if no elements are higher.
define <4 x i32> @test_vchfs_none_store(<4 x i32> %a, <4 x i32> %b, ptr %ptr) {
; CHECK-LABEL: test_vchfs_none_store:
-; CHECK-NOT: %r
-; CHECK: vchfs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchfs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB172_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2080,10 +2266,11 @@ exit:
; VCHGS with no processing of the result.
define i32 @test_vchgs(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vchgs:
-; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchgs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
ret i32 %res
@@ -2092,10 +2279,11 @@ define i32 @test_vchgs(<2 x i64> %a, <2 x i64> %b) {
; VCHGS returning 1 if all elements are higher (CC == 0).
define i32 @test_vchgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vchgs_all_bool:
-; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochie %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchgs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochie %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
%cmp = icmp ult i32 %res, 1
@@ -2106,11 +2294,12 @@ define i32 @test_vchgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; VCHGS, storing to %ptr if all elements are higher.
define <2 x i64> @test_vchgs_all_store(<2 x i64> %a, <2 x i64> %b, ptr %ptr) {
; CHECK-LABEL: test_vchgs_all_store:
-; CHECK-NOT: %r
-; CHECK: vchgs %v24, %v24, %v26
-; CHECK-NEXT: {{bnher|bner}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchgs %v24, %v24, %v26
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB175_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 0
%cc = extractvalue {<2 x i64>, i32} %call, 1
@@ -2128,10 +2317,11 @@ exit:
; VCHLBS with no processing of the result.
define i32 @test_vchlbs(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vchlbs:
-; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
ret i32 %res
@@ -2140,10 +2330,11 @@ define i32 @test_vchlbs(<16 x i8> %a, <16 x i8> %b) {
; VCHLBS, returning 1 if any elements are higher (CC != 3).
define i32 @test_vchlbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vchlbs_any_bool:
-; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochile %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochile %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 1
%cmp = icmp ne i32 %res, 3
@@ -2154,11 +2345,12 @@ define i32 @test_vchlbs_any_bool(<16 x i8> %a, <16 x i8> %b) {
; VCHLBS, storing to %ptr if any elements are higher.
define <16 x i8> @test_vchlbs_any_store(<16 x i8> %a, <16 x i8> %b, ptr %ptr) {
; CHECK-LABEL: test_vchlbs_any_store:
-; CHECK-NOT: %r
-; CHECK: vchlbs %v24, %v24, %v26
-; CHECK-NEXT: {{bor|bnler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlbs %v24, %v24, %v26
+; CHECK-NEXT: bor %r14
+; CHECK-NEXT: .LBB178_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -2176,10 +2368,11 @@ exit:
; VCHLHS with no processing of the result.
define i32 @test_vchlhs(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vchlhs:
-; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlhs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
ret i32 %res
@@ -2188,10 +2381,11 @@ define i32 @test_vchlhs(<8 x i16> %a, <8 x i16> %b) {
; VCHLHS, returning 1 if not all elements are higher.
define i32 @test_vchlhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vchlhs_notall_bool:
-; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochinhe %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlhs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochinhe %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 1
%cmp = icmp uge i32 %res, 1
@@ -2201,13 +2395,14 @@ define i32 @test_vchlhs_notall_bool(<8 x i16> %a, <8 x i16> %b) {
; VCHLHS, storing to %ptr if not all elements are higher.
define <8 x i16> @test_vchlhs_notall_store(<8 x i16> %a, <8 x i16> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vchlhs_notall_store:
-; CHECK-NOT: %r
-; CHECK: vchlhs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlhs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB181_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2225,10 +2420,11 @@ exit:
; VCHLFS with no processing of the result.
define i32 @test_vchlfs(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vchlfs:
-; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlfs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
ret i32 %res
@@ -2237,10 +2433,11 @@ define i32 @test_vchlfs(<4 x i32> %a, <4 x i32> %b) {
; VCHLFS, returning 1 if no elements are higher.
define i32 @test_vchlfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vchlfs_none_bool:
-; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochio %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlfs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochio %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
%cmp = icmp eq i32 %res, 3
@@ -2250,13 +2447,14 @@ define i32 @test_vchlfs_none_bool(<4 x i32> %a, <4 x i32> %b) {
; VCHLFS, storing to %ptr if no elements are higher.
define <4 x i32> @test_vchlfs_none_store(<4 x i32> %a, <4 x i32> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vchlfs_none_store:
-; CHECK-NOT: %r
-; CHECK: vchlfs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlfs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB184_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2274,10 +2472,11 @@ exit:
; VCHLGS with no processing of the result.
define i32 @test_vchlgs(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vchlgs:
-; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlgs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
ret i32 %res
@@ -2286,10 +2485,11 @@ define i32 @test_vchlgs(<2 x i64> %a, <2 x i64> %b) {
; VCHLGS returning 1 if all elements are higher (CC == 0).
define i32 @test_vchlgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vchlgs_all_bool:
-; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochie %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlgs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochie %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
%cmp = icmp slt i32 %res, 1
@@ -2300,11 +2500,12 @@ define i32 @test_vchlgs_all_bool(<2 x i64> %a, <2 x i64> %b) {
; VCHLGS, storing to %ptr if all elements are higher.
define <2 x i64> @test_vchlgs_all_store(<2 x i64> %a, <2 x i64> %b, ptr %ptr) {
; CHECK-LABEL: test_vchlgs_all_store:
-; CHECK-NOT: %r
-; CHECK: vchlgs %v24, %v24, %v26
-; CHECK-NEXT: {{bnher|bner}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vchlgs %v24, %v24, %v26
+; CHECK-NEXT: bnher %r14
+; CHECK-NEXT: .LBB187_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
%res = extractvalue {<2 x i64>, i32} %call, 0
%cc = extractvalue {<2 x i64>, i32} %call, 1
@@ -2322,8 +2523,9 @@ exit:
; VFAEB with !IN !RT.
define <16 x i8> @test_vfaeb_0(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaeb_0:
-; CHECK: vfaeb %v24, %v24, %v26, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaeb %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 0)
ret <16 x i8> %res
}
@@ -2331,8 +2533,9 @@ define <16 x i8> @test_vfaeb_0(<16 x i8> %a, <16 x i8> %b) {
; VFAEB with !IN RT.
define <16 x i8> @test_vfaeb_4(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaeb_4:
-; CHECK: vfaeb %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaeb %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 4)
ret <16 x i8> %res
}
@@ -2340,8 +2543,9 @@ define <16 x i8> @test_vfaeb_4(<16 x i8> %a, <16 x i8> %b) {
; VFAEB with IN !RT.
define <16 x i8> @test_vfaeb_8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaeb_8:
-; CHECK: vfaeb %v24, %v24, %v26, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaeb %v24, %v24, %v26, 8
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 8)
ret <16 x i8> %res
}
@@ -2349,8 +2553,9 @@ define <16 x i8> @test_vfaeb_8(<16 x i8> %a, <16 x i8> %b) {
; VFAEB with IN RT.
define <16 x i8> @test_vfaeb_12(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaeb_12:
-; CHECK: vfaeb %v24, %v24, %v26, 12
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaeb %v24, %v24, %v26, 12
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 12)
ret <16 x i8> %res
}
@@ -2358,8 +2563,9 @@ define <16 x i8> @test_vfaeb_12(<16 x i8> %a, <16 x i8> %b) {
; VFAEB with CS -- should be ignored.
define <16 x i8> @test_vfaeb_1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaeb_1:
-; CHECK: vfaeb %v24, %v24, %v26, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaeb %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 1)
ret <16 x i8> %res
}
@@ -2367,8 +2573,9 @@ define <16 x i8> @test_vfaeb_1(<16 x i8> %a, <16 x i8> %b) {
; VFAEH.
define <8 x i16> @test_vfaeh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vfaeh:
-; CHECK: vfaeh %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaeh %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vfaeh(<8 x i16> %a, <8 x i16> %b, i32 4)
ret <8 x i16> %res
}
@@ -2376,8 +2583,9 @@ define <8 x i16> @test_vfaeh(<8 x i16> %a, <8 x i16> %b) {
; VFAEF.
define <4 x i32> @test_vfaef(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vfaef:
-; CHECK: vfaef %v24, %v24, %v26, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaef %v24, %v24, %v26, 8
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vfaef(<4 x i32> %a, <4 x i32> %b, i32 8)
ret <4 x i32> %res
}
@@ -2385,11 +2593,12 @@ define <4 x i32> @test_vfaef(<4 x i32> %a, <4 x i32> %b) {
; VFAEBS.
define <16 x i8> @test_vfaebs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfaebs:
-; CHECK: vfaebs %v24, %v24, %v26, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaebs %v24, %v24, %v26, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8> %a, <16 x i8> %b,
i32 0)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -2401,11 +2610,12 @@ define <16 x i8> @test_vfaebs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; VFAEHS.
define <8 x i16> @test_vfaehs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfaehs:
-; CHECK: vfaehs %v24, %v24, %v26, 4
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaehs %v24, %v24, %v26, 4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16> %a, <8 x i16> %b,
i32 4)
%res = extractvalue {<8 x i16>, i32} %call, 0
@@ -2417,11 +2627,12 @@ define <8 x i16> @test_vfaehs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VFAEFS.
define <4 x i32> @test_vfaefs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfaefs:
-; CHECK: vfaefs %v24, %v24, %v26, 8
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaefs %v24, %v24, %v26, 8
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32> %a, <4 x i32> %b,
i32 8)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -2433,8 +2644,9 @@ define <4 x i32> @test_vfaefs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VFAEZB with !IN !RT.
define <16 x i8> @test_vfaezb_0(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaezb_0:
-; CHECK: vfaezb %v24, %v24, %v26, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezb %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 0)
ret <16 x i8> %res
}
@@ -2442,8 +2654,9 @@ define <16 x i8> @test_vfaezb_0(<16 x i8> %a, <16 x i8> %b) {
; VFAEZB with !IN RT.
define <16 x i8> @test_vfaezb_4(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaezb_4:
-; CHECK: vfaezb %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezb %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 4)
ret <16 x i8> %res
}
@@ -2451,8 +2664,9 @@ define <16 x i8> @test_vfaezb_4(<16 x i8> %a, <16 x i8> %b) {
; VFAEZB with IN !RT.
define <16 x i8> @test_vfaezb_8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaezb_8:
-; CHECK: vfaezb %v24, %v24, %v26, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezb %v24, %v24, %v26, 8
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 8)
ret <16 x i8> %res
}
@@ -2460,8 +2674,9 @@ define <16 x i8> @test_vfaezb_8(<16 x i8> %a, <16 x i8> %b) {
; VFAEZB with IN RT.
define <16 x i8> @test_vfaezb_12(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaezb_12:
-; CHECK: vfaezb %v24, %v24, %v26, 12
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezb %v24, %v24, %v26, 12
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 12)
ret <16 x i8> %res
}
@@ -2469,8 +2684,9 @@ define <16 x i8> @test_vfaezb_12(<16 x i8> %a, <16 x i8> %b) {
; VFAEZB with CS -- should be ignored.
define <16 x i8> @test_vfaezb_1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfaezb_1:
-; CHECK: vfaezb %v24, %v24, %v26, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezb %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 1)
ret <16 x i8> %res
}
@@ -2478,8 +2694,9 @@ define <16 x i8> @test_vfaezb_1(<16 x i8> %a, <16 x i8> %b) {
; VFAEZH.
define <8 x i16> @test_vfaezh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vfaezh:
-; CHECK: vfaezh %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezh %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vfaezh(<8 x i16> %a, <8 x i16> %b, i32 4)
ret <8 x i16> %res
}
@@ -2487,8 +2704,9 @@ define <8 x i16> @test_vfaezh(<8 x i16> %a, <8 x i16> %b) {
; VFAEZF.
define <4 x i32> @test_vfaezf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vfaezf:
-; CHECK: vfaezf %v24, %v24, %v26, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezf %v24, %v24, %v26, 8
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vfaezf(<4 x i32> %a, <4 x i32> %b, i32 8)
ret <4 x i32> %res
}
@@ -2496,11 +2714,12 @@ define <4 x i32> @test_vfaezf(<4 x i32> %a, <4 x i32> %b) {
; VFAEZBS.
define <16 x i8> @test_vfaezbs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfaezbs:
-; CHECK: vfaezbs %v24, %v24, %v26, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezbs %v24, %v24, %v26, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8> %a, <16 x i8> %b,
i32 0)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -2512,11 +2731,12 @@ define <16 x i8> @test_vfaezbs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; VFAEZHS.
define <8 x i16> @test_vfaezhs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfaezhs:
-; CHECK: vfaezhs %v24, %v24, %v26, 4
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezhs %v24, %v24, %v26, 4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16> %a, <8 x i16> %b,
i32 4)
%res = extractvalue {<8 x i16>, i32} %call, 0
@@ -2528,11 +2748,12 @@ define <8 x i16> @test_vfaezhs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VFAEZFS.
define <4 x i32> @test_vfaezfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfaezfs:
-; CHECK: vfaezfs %v24, %v24, %v26, 8
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfaezfs %v24, %v24, %v26, 8
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32> %a, <4 x i32> %b,
i32 8)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -2544,8 +2765,9 @@ define <4 x i32> @test_vfaezfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VFEEB.
define <16 x i8> @test_vfeeb_0(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfeeb_0:
-; CHECK: vfeeb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeeb %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfeeb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -2553,8 +2775,9 @@ define <16 x i8> @test_vfeeb_0(<16 x i8> %a, <16 x i8> %b) {
; VFEEH.
define <8 x i16> @test_vfeeh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vfeeh:
-; CHECK: vfeeh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeeh %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vfeeh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -2562,8 +2785,9 @@ define <8 x i16> @test_vfeeh(<8 x i16> %a, <8 x i16> %b) {
; VFEEF.
define <4 x i32> @test_vfeef(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vfeef:
-; CHECK: vfeef %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeef %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vfeef(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -2571,11 +2795,12 @@ define <4 x i32> @test_vfeef(<4 x i32> %a, <4 x i32> %b) {
; VFEEBS.
define <16 x i8> @test_vfeebs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfeebs:
-; CHECK: vfeebs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeebs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -2586,11 +2811,12 @@ define <16 x i8> @test_vfeebs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; VFEEHS.
define <8 x i16> @test_vfeehs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfeehs:
-; CHECK: vfeehs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeehs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2601,11 +2827,12 @@ define <8 x i16> @test_vfeehs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VFEEFS.
define <4 x i32> @test_vfeefs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfeefs:
-; CHECK: vfeefs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeefs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2616,8 +2843,9 @@ define <4 x i32> @test_vfeefs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VFEEZB.
define <16 x i8> @test_vfeezb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfeezb:
-; CHECK: vfeezb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeezb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfeezb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -2625,8 +2853,9 @@ define <16 x i8> @test_vfeezb(<16 x i8> %a, <16 x i8> %b) {
; VFEEZH.
define <8 x i16> @test_vfeezh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vfeezh:
-; CHECK: vfeezh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeezh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vfeezh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -2634,8 +2863,9 @@ define <8 x i16> @test_vfeezh(<8 x i16> %a, <8 x i16> %b) {
; VFEEZF.
define <4 x i32> @test_vfeezf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vfeezf:
-; CHECK: vfeezf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeezf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vfeezf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -2643,11 +2873,12 @@ define <4 x i32> @test_vfeezf(<4 x i32> %a, <4 x i32> %b) {
; VFEEZBS.
define <16 x i8> @test_vfeezbs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfeezbs:
-; CHECK: vfeezbs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeezbs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -2658,11 +2889,12 @@ define <16 x i8> @test_vfeezbs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; VFEEZHS.
define <8 x i16> @test_vfeezhs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfeezhs:
-; CHECK: vfeezhs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeezhs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2673,11 +2905,12 @@ define <8 x i16> @test_vfeezhs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VFEEZFS.
define <4 x i32> @test_vfeezfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfeezfs:
-; CHECK: vfeezfs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeezfs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2688,8 +2921,9 @@ define <4 x i32> @test_vfeezfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VFENEB.
define <16 x i8> @test_vfeneb_0(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfeneb_0:
-; CHECK: vfeneb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeneb %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfeneb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -2697,8 +2931,9 @@ define <16 x i8> @test_vfeneb_0(<16 x i8> %a, <16 x i8> %b) {
; VFENEH.
define <8 x i16> @test_vfeneh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vfeneh:
-; CHECK: vfeneh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfeneh %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vfeneh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -2706,8 +2941,9 @@ define <8 x i16> @test_vfeneh(<8 x i16> %a, <8 x i16> %b) {
; VFENEF.
define <4 x i32> @test_vfenef(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vfenef:
-; CHECK: vfenef %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenef %v24, %v24, %v26, 0
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vfenef(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -2715,11 +2951,12 @@ define <4 x i32> @test_vfenef(<4 x i32> %a, <4 x i32> %b) {
; VFENEBS.
define <16 x i8> @test_vfenebs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfenebs:
-; CHECK: vfenebs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenebs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -2730,11 +2967,12 @@ define <16 x i8> @test_vfenebs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; VFENEHS.
define <8 x i16> @test_vfenehs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfenehs:
-; CHECK: vfenehs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenehs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2745,11 +2983,12 @@ define <8 x i16> @test_vfenehs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VFENEFS.
define <4 x i32> @test_vfenefs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfenefs:
-; CHECK: vfenefs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenefs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2760,8 +2999,9 @@ define <4 x i32> @test_vfenefs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VFENEZB.
define <16 x i8> @test_vfenezb(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vfenezb:
-; CHECK: vfenezb %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenezb %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vfenezb(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %res
}
@@ -2769,8 +3009,9 @@ define <16 x i8> @test_vfenezb(<16 x i8> %a, <16 x i8> %b) {
; VFENEZH.
define <8 x i16> @test_vfenezh(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vfenezh:
-; CHECK: vfenezh %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenezh %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vfenezh(<8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %res
}
@@ -2778,8 +3019,9 @@ define <8 x i16> @test_vfenezh(<8 x i16> %a, <8 x i16> %b) {
; VFENEZF.
define <4 x i32> @test_vfenezf(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vfenezf:
-; CHECK: vfenezf %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenezf %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vfenezf(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %res
}
@@ -2787,11 +3029,12 @@ define <4 x i32> @test_vfenezf(<4 x i32> %a, <4 x i32> %b) {
; VFENEZBS.
define <16 x i8> @test_vfenezbs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfenezbs:
-; CHECK: vfenezbs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenezbs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8> %a, <16 x i8> %b)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -2802,11 +3045,12 @@ define <16 x i8> @test_vfenezbs(<16 x i8> %a, <16 x i8> %b, ptr %ccptr) {
; VFENEZHS.
define <8 x i16> @test_vfenezhs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfenezhs:
-; CHECK: vfenezhs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenezhs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16> %a, <8 x i16> %b)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2817,11 +3061,12 @@ define <8 x i16> @test_vfenezhs(<8 x i16> %a, <8 x i16> %b, ptr %ccptr) {
; VFENEZFS.
define <4 x i32> @test_vfenezfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; CHECK-LABEL: test_vfenezfs:
-; CHECK: vfenezfs %v24, %v24, %v26
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfenezfs %v24, %v24, %v26
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32> %a, <4 x i32> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2832,8 +3077,9 @@ define <4 x i32> @test_vfenezfs(<4 x i32> %a, <4 x i32> %b, ptr %ccptr) {
; VISTRB.
define <16 x i8> @test_vistrb(<16 x i8> %a) {
; CHECK-LABEL: test_vistrb:
-; CHECK: vistrb %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vistrb %v24, %v24, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vistrb(<16 x i8> %a)
ret <16 x i8> %res
}
@@ -2841,8 +3087,9 @@ define <16 x i8> @test_vistrb(<16 x i8> %a) {
; VISTRH.
define <8 x i16> @test_vistrh(<8 x i16> %a) {
; CHECK-LABEL: test_vistrh:
-; CHECK: vistrh %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vistrh %v24, %v24, 0
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vistrh(<8 x i16> %a)
ret <8 x i16> %res
}
@@ -2850,8 +3097,9 @@ define <8 x i16> @test_vistrh(<8 x i16> %a) {
; VISTRF.
define <4 x i32> @test_vistrf(<4 x i32> %a) {
; CHECK-LABEL: test_vistrf:
-; CHECK: vistrf %v24, %v24
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vistrf %v24, %v24, 0
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vistrf(<4 x i32> %a)
ret <4 x i32> %res
}
@@ -2859,11 +3107,12 @@ define <4 x i32> @test_vistrf(<4 x i32> %a) {
; VISTRBS.
define <16 x i8> @test_vistrbs(<16 x i8> %a, ptr %ccptr) {
; CHECK-LABEL: test_vistrbs:
-; CHECK: vistrbs %v24, %v24
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vistrbs %v24, %v24
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8> %a)
%res = extractvalue {<16 x i8>, i32} %call, 0
%cc = extractvalue {<16 x i8>, i32} %call, 1
@@ -2874,11 +3123,12 @@ define <16 x i8> @test_vistrbs(<16 x i8> %a, ptr %ccptr) {
; VISTRHS.
define <8 x i16> @test_vistrhs(<8 x i16> %a, ptr %ccptr) {
; CHECK-LABEL: test_vistrhs:
-; CHECK: vistrhs %v24, %v24
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vistrhs %v24, %v24
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16> %a)
%res = extractvalue {<8 x i16>, i32} %call, 0
%cc = extractvalue {<8 x i16>, i32} %call, 1
@@ -2889,11 +3139,12 @@ define <8 x i16> @test_vistrhs(<8 x i16> %a, ptr %ccptr) {
; VISTRFS.
define <4 x i32> @test_vistrfs(<4 x i32> %a, ptr %ccptr) {
; CHECK-LABEL: test_vistrfs:
-; CHECK: vistrfs %v24, %v24
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vistrfs %v24, %v24
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32> %a)
%res = extractvalue {<4 x i32>, i32} %call, 0
%cc = extractvalue {<4 x i32>, i32} %call, 1
@@ -2904,8 +3155,9 @@ define <4 x i32> @test_vistrfs(<4 x i32> %a, ptr %ccptr) {
; VSTRCB with !IN !RT.
define <16 x i8> @test_vstrcb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrcb_0:
-; CHECK: vstrcb %v24, %v24, %v26, %v28, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcb %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 0)
ret <16 x i8> %res
@@ -2914,8 +3166,9 @@ define <16 x i8> @test_vstrcb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCB with !IN RT.
define <16 x i8> @test_vstrcb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrcb_4:
-; CHECK: vstrcb %v24, %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcb %v24, %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 4)
ret <16 x i8> %res
@@ -2924,8 +3177,9 @@ define <16 x i8> @test_vstrcb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCB with IN !RT.
define <16 x i8> @test_vstrcb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrcb_8:
-; CHECK: vstrcb %v24, %v24, %v26, %v28, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcb %v24, %v24, %v26, %v28, 8
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 8)
ret <16 x i8> %res
@@ -2934,8 +3188,9 @@ define <16 x i8> @test_vstrcb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCB with IN RT.
define <16 x i8> @test_vstrcb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrcb_12:
-; CHECK: vstrcb %v24, %v24, %v26, %v28, 12
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcb %v24, %v24, %v26, %v28, 12
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 12)
ret <16 x i8> %res
@@ -2944,8 +3199,9 @@ define <16 x i8> @test_vstrcb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCB with CS -- should be ignored.
define <16 x i8> @test_vstrcb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrcb_1:
-; CHECK: vstrcb %v24, %v24, %v26, %v28, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcb %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 1)
ret <16 x i8> %res
@@ -2954,8 +3210,9 @@ define <16 x i8> @test_vstrcb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCH.
define <8 x i16> @test_vstrch(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vstrch:
-; CHECK: vstrch %v24, %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrch %v24, %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vstrch(<8 x i16> %a, <8 x i16> %b,
<8 x i16> %c, i32 4)
ret <8 x i16> %res
@@ -2964,8 +3221,9 @@ define <8 x i16> @test_vstrch(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; VSTRCF.
define <4 x i32> @test_vstrcf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vstrcf:
-; CHECK: vstrcf %v24, %v24, %v26, %v28, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcf %v24, %v24, %v26, %v28, 8
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vstrcf(<4 x i32> %a, <4 x i32> %b,
<4 x i32> %c, i32 8)
ret <4 x i32> %res
@@ -2973,13 +3231,14 @@ define <4 x i32> @test_vstrcf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; VSTRCBS.
define <16 x i8> @test_vstrcbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrcbs:
-; CHECK: vstrcbs %v24, %v24, %v26, %v28, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcbs %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 0)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -2990,13 +3249,14 @@ define <16 x i8> @test_vstrcbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
; VSTRCHS.
define <8 x i16> @test_vstrchs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrchs:
-; CHECK: vstrchs %v24, %v24, %v26, %v28, 4
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrchs %v24, %v24, %v26, %v28, 4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16> %a, <8 x i16> %b,
<8 x i16> %c, i32 4)
%res = extractvalue {<8 x i16>, i32} %call, 0
@@ -3007,13 +3267,14 @@ define <8 x i16> @test_vstrchs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c,
; VSTRCFS.
define <4 x i32> @test_vstrcfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrcfs:
-; CHECK: vstrcfs %v24, %v24, %v26, %v28, 8
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrcfs %v24, %v24, %v26, %v28, 8
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32> %a, <4 x i32> %b,
<4 x i32> %c, i32 8)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -3025,8 +3286,9 @@ define <4 x i32> @test_vstrcfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
; VSTRCZB with !IN !RT.
define <16 x i8> @test_vstrczb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrczb_0:
-; CHECK: vstrczb %v24, %v24, %v26, %v28, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczb %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 0)
ret <16 x i8> %res
@@ -3035,8 +3297,9 @@ define <16 x i8> @test_vstrczb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCZB with !IN RT.
define <16 x i8> @test_vstrczb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrczb_4:
-; CHECK: vstrczb %v24, %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczb %v24, %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 4)
ret <16 x i8> %res
@@ -3045,8 +3308,9 @@ define <16 x i8> @test_vstrczb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCZB with IN !RT.
define <16 x i8> @test_vstrczb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrczb_8:
-; CHECK: vstrczb %v24, %v24, %v26, %v28, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczb %v24, %v24, %v26, %v28, 8
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 8)
ret <16 x i8> %res
@@ -3055,8 +3319,9 @@ define <16 x i8> @test_vstrczb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCZB with IN RT.
define <16 x i8> @test_vstrczb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrczb_12:
-; CHECK: vstrczb %v24, %v24, %v26, %v28, 12
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczb %v24, %v24, %v26, %v28, 12
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 12)
ret <16 x i8> %res
@@ -3065,8 +3330,9 @@ define <16 x i8> @test_vstrczb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCZB with CS -- should be ignored.
define <16 x i8> @test_vstrczb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vstrczb_1:
-; CHECK: vstrczb %v24, %v24, %v26, %v28, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczb %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 1)
ret <16 x i8> %res
@@ -3075,8 +3341,9 @@ define <16 x i8> @test_vstrczb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; VSTRCZH.
define <8 x i16> @test_vstrczh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; CHECK-LABEL: test_vstrczh:
-; CHECK: vstrczh %v24, %v24, %v26, %v28, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczh %v24, %v24, %v26, %v28, 4
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vstrczh(<8 x i16> %a, <8 x i16> %b,
<8 x i16> %c, i32 4)
ret <8 x i16> %res
@@ -3085,8 +3352,9 @@ define <8 x i16> @test_vstrczh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; VSTRCZF.
define <4 x i32> @test_vstrczf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: test_vstrczf:
-; CHECK: vstrczf %v24, %v24, %v26, %v28, 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczf %v24, %v24, %v26, %v28, 8
+; CHECK-NEXT: br %r14
%res = call <4 x i32> @llvm.s390.vstrczf(<4 x i32> %a, <4 x i32> %b,
<4 x i32> %c, i32 8)
ret <4 x i32> %res
@@ -3094,13 +3362,14 @@ define <4 x i32> @test_vstrczf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; VSTRCZBS.
define <16 x i8> @test_vstrczbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrczbs:
-; CHECK: vstrczbs %v24, %v24, %v26, %v28, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczbs %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c, i32 0)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -3111,13 +3380,14 @@ define <16 x i8> @test_vstrczbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
; VSTRCZHS.
define <8 x i16> @test_vstrczhs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrczhs:
-; CHECK: vstrczhs %v24, %v24, %v26, %v28, 4
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczhs %v24, %v24, %v26, %v28, 4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16> %a, <8 x i16> %b,
<8 x i16> %c, i32 4)
%res = extractvalue {<8 x i16>, i32} %call, 0
@@ -3128,13 +3398,14 @@ define <8 x i16> @test_vstrczhs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c,
; VSTRCZFS.
define <4 x i32> @test_vstrczfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrczfs:
-; CHECK: vstrczfs %v24, %v24, %v26, %v28, 8
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrczfs %v24, %v24, %v26, %v28, 8
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32> %a, <4 x i32> %b,
<4 x i32> %c, i32 8)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -3146,10 +3417,11 @@ define <4 x i32> @test_vstrczfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c,
; VFCEDBS with no processing of the result.
define i32 @test_vfcedbs(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfcedbs:
-; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcedbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3159,10 +3431,11 @@ define i32 @test_vfcedbs(<2 x double> %a, <2 x double> %b) {
; VFCEDBS, returning 1 if any elements are equal (CC != 3).
define i32 @test_vfcedbs_any_bool(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfcedbs_any_bool:
-; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochile %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcedbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochile %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3173,13 +3446,14 @@ define i32 @test_vfcedbs_any_bool(<2 x double> %a, <2 x double> %b) {
; VFCEDBS, storing to %ptr if any elements are equal.
define <2 x i64> @test_vfcedbs_any_store(<2 x double> %a, <2 x double> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vfcedbs_any_store:
-; CHECK-NOT: %r
-; CHECK: vfcedbs %v24, %v24, %v26
-; CHECK-NEXT: {{bor|bnler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcedbs %v24, %v24, %v26
+; CHECK-NEXT: bor %r14
+; CHECK-NEXT: .LBB260_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 0
@@ -3198,10 +3472,11 @@ exit:
; VFCHDBS with no processing of the result.
define i32 @test_vfchdbs(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfchdbs:
-; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchdbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3211,10 +3486,11 @@ define i32 @test_vfchdbs(<2 x double> %a, <2 x double> %b) {
; VFCHDBS, returning 1 if not all elements are higher.
define i32 @test_vfchdbs_notall_bool(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfchdbs_notall_bool:
-; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochinhe %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchdbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochinhe %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3225,13 +3501,14 @@ define i32 @test_vfchdbs_notall_bool(<2 x double> %a, <2 x double> %b) {
; VFCHDBS, storing to %ptr if not all elements are higher.
define <2 x i64> @test_vfchdbs_notall_store(<2 x double> %a, <2 x double> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vfchdbs_notall_store:
-; CHECK-NOT: %r
-; CHECK: vfchdbs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchdbs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB263_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 0
@@ -3250,10 +3527,11 @@ exit:
; VFCHEDBS with no processing of the result.
define i32 @test_vfchedbs(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfchedbs:
-; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchedbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3263,10 +3541,11 @@ define i32 @test_vfchedbs(<2 x double> %a, <2 x double> %b) {
; VFCHEDBS, returning 1 if neither element is higher or equal.
define i32 @test_vfchedbs_none_bool(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfchedbs_none_bool:
-; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochio %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchedbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochio %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 1
@@ -3277,13 +3556,14 @@ define i32 @test_vfchedbs_none_bool(<2 x double> %a, <2 x double> %b) {
; VFCHEDBS, storing to %ptr if neither element is higher or equal.
define <2 x i64> @test_vfchedbs_none_store(<2 x double> %a, <2 x double> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vfchedbs_none_store:
-; CHECK-NOT: %r
-; CHECK: vfchedbs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchedbs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB266_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
<2 x double> %b)
%res = extractvalue {<2 x i64>, i32} %call, 0
@@ -3302,10 +3582,11 @@ exit:
; VFTCIDB with the lowest useful class selector and no processing of the result.
define i32 @test_vftcidb(<2 x double> %a) {
; CHECK-LABEL: test_vftcidb:
-; CHECK: vftcidb {{%v[0-9]+}}, %v24, 1
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vftcidb %v0, %v24, 1
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 1)
%res = extractvalue {<2 x i64>, i32} %call, 1
ret i32 %res
@@ -3315,10 +3596,11 @@ define i32 @test_vftcidb(<2 x double> %a) {
; have the right class (CC == 0).
define i32 @test_vftcidb_all_bool(<2 x double> %a) {
; CHECK-LABEL: test_vftcidb_all_bool:
-; CHECK: vftcidb {{%v[0-9]+}}, %v24, 4094
-; CHECK: lhi %r2, 0
-; CHECK: lochie %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vftcidb %v0, %v24, 4094
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochie %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 4094)
%res = extractvalue {<2 x i64>, i32} %call, 1
%cmp = icmp eq i32 %res, 0
@@ -3329,8 +3611,9 @@ define i32 @test_vftcidb_all_bool(<2 x double> %a) {
; VFIDB with a rounding mode not usable via standard intrinsics.
define <2 x double> @test_vfidb_0_4(<2 x double> %a) {
; CHECK-LABEL: test_vfidb_0_4:
-; CHECK: vfidb %v24, %v24, 0, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfidb %v24, %v24, 0, 4
+; CHECK-NEXT: br %r14
%res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 0, i32 4)
ret <2 x double> %res
}
@@ -3338,8 +3621,9 @@ define <2 x double> @test_vfidb_0_4(<2 x double> %a) {
; VFIDB with IEEE-inexact exception suppressed.
define <2 x double> @test_vfidb_4_0(<2 x double> %a) {
; CHECK-LABEL: test_vfidb_4_0:
-; CHECK: vfidb %v24, %v24, 4, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfidb %v24, %v24, 4, 0
+; CHECK-NEXT: br %r14
%res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 4, i32 0)
ret <2 x double> %res
}
diff --git a/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll b/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll
index b93a610aa0b1a..9da1cee3bb4fe 100644
--- a/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector intrinsics added with z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
@@ -21,8 +22,9 @@ declare <4 x float> @llvm.s390.vfminsb(<4 x float>, <4 x float>, i32)
; VBPERM.
define <2 x i64> @test_vbperm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vbperm:
-; CHECK: vbperm %v24, %v24, %v26
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vbperm %v24, %v24, %v26
+; CHECK-NEXT: br %r14
%res = call <2 x i64> @llvm.s390.vbperm(<16 x i8> %a, <16 x i8> %b)
ret <2 x i64> %res
}
@@ -30,8 +32,9 @@ define <2 x i64> @test_vbperm(<16 x i8> %a, <16 x i8> %b) {
; VMSLG with no shifts.
define <16 x i8> @test_vmslg1(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vmslg1:
-; CHECK: vmslg %v24, %v24, %v26, %v28, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmslg %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 0)
ret <16 x i8> %res
}
@@ -39,8 +42,9 @@ define <16 x i8> @test_vmslg1(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
; VMSLG with both shifts.
define <16 x i8> @test_vmslg2(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
; CHECK-LABEL: test_vmslg2:
-; CHECK: vmslg %v24, %v24, %v26, %v28, 12
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmslg %v24, %v24, %v26, %v28, 12
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 12)
ret <16 x i8> %res
}
@@ -48,8 +52,9 @@ define <16 x i8> @test_vmslg2(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) {
; VLRLR with the lowest in-range displacement.
define <16 x i8> @test_vlrlr1(ptr %ptr, i32 %length) {
; CHECK-LABEL: test_vlrlr1:
-; CHECK: vlrlr %v24, %r3, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlrlr %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr)
ret <16 x i8> %res
}
@@ -57,8 +62,9 @@ define <16 x i8> @test_vlrlr1(ptr %ptr, i32 %length) {
; VLRLR with the highest in-range displacement.
define <16 x i8> @test_vlrlr2(ptr %base, i32 %length) {
; CHECK-LABEL: test_vlrlr2:
-; CHECK: vlrlr %v24, %r3, 4095(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlrlr %v24, %r3, 4095(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4095
%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr)
ret <16 x i8> %res
@@ -67,8 +73,10 @@ define <16 x i8> @test_vlrlr2(ptr %base, i32 %length) {
; VLRLR with an out-of-range displacement.
define <16 x i8> @test_vlrlr3(ptr %base, i32 %length) {
; CHECK-LABEL: test_vlrlr3:
-; CHECK: vlrlr %v24, %r3, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlrlr %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr)
ret <16 x i8> %res
@@ -77,8 +85,10 @@ define <16 x i8> @test_vlrlr3(ptr %base, i32 %length) {
; Check that VLRLR doesn't allow an index.
define <16 x i8> @test_vlrlr4(ptr %base, i64 %index, i32 %length) {
; CHECK-LABEL: test_vlrlr4:
-; CHECK: vlrlr %v24, %r4, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r2, %r3
+; CHECK-NEXT: vlrlr %v24, %r4, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 %index
%res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr)
ret <16 x i8> %res
@@ -87,8 +97,9 @@ define <16 x i8> @test_vlrlr4(ptr %base, i64 %index, i32 %length) {
; VLRL with the lowest in-range displacement.
define <16 x i8> @test_vlrl1(ptr %ptr) {
; CHECK-LABEL: test_vlrl1:
-; CHECK: vlrl %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlrl %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr)
ret <16 x i8> %res
}
@@ -96,8 +107,9 @@ define <16 x i8> @test_vlrl1(ptr %ptr) {
; VLRL with the highest in-range displacement.
define <16 x i8> @test_vlrl2(ptr %base) {
; CHECK-LABEL: test_vlrl2:
-; CHECK: vlrl %v24, 4095(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlrl %v24, 4095(%r2), 0
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4095
%res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr)
ret <16 x i8> %res
@@ -106,8 +118,10 @@ define <16 x i8> @test_vlrl2(ptr %base) {
; VLRL with an out-of-range displacement.
define <16 x i8> @test_vlrl3(ptr %base) {
; CHECK-LABEL: test_vlrl3:
-; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlrl %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
%res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr)
ret <16 x i8> %res
@@ -116,8 +130,10 @@ define <16 x i8> @test_vlrl3(ptr %base) {
; Check that VLRL doesn't allow an index.
define <16 x i8> @test_vlrl4(ptr %base, i64 %index) {
; CHECK-LABEL: test_vlrl4:
-; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r2, %r3
+; CHECK-NEXT: vlrl %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 %index
%res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr)
ret <16 x i8> %res
@@ -126,8 +142,9 @@ define <16 x i8> @test_vlrl4(ptr %base, i64 %index) {
; VLRL with length >= 15 should become VL.
define <16 x i8> @test_vlrl5(ptr %ptr) {
; CHECK-LABEL: test_vlrl5:
-; CHECK: vl %v24, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v24, 0(%r2), 3
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vlrl(i32 15, ptr %ptr)
ret <16 x i8> %res
}
@@ -135,8 +152,9 @@ define <16 x i8> @test_vlrl5(ptr %ptr) {
; VSTRLR with the lowest in-range displacement.
define void @test_vstrlr1(<16 x i8> %vec, ptr %ptr, i32 %length) {
; CHECK-LABEL: test_vstrlr1:
-; CHECK: vstrlr %v24, %r3, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrlr %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
}
@@ -144,8 +162,9 @@ define void @test_vstrlr1(<16 x i8> %vec, ptr %ptr, i32 %length) {
; VSTRLR with the highest in-range displacement.
define void @test_vstrlr2(<16 x i8> %vec, ptr %base, i32 %length) {
; CHECK-LABEL: test_vstrlr2:
-; CHECK: vstrlr %v24, %r3, 4095(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrlr %v24, %r3, 4095(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4095
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
@@ -154,8 +173,10 @@ define void @test_vstrlr2(<16 x i8> %vec, ptr %base, i32 %length) {
; VSTRLR with an out-of-range displacement.
define void @test_vstrlr3(<16 x i8> %vec, ptr %base, i32 %length) {
; CHECK-LABEL: test_vstrlr3:
-; CHECK: vstrlr %v24, %r3, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstrlr %v24, %r3, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
@@ -164,8 +185,10 @@ define void @test_vstrlr3(<16 x i8> %vec, ptr %base, i32 %length) {
; Check that VSTRLR doesn't allow an index.
define void @test_vstrlr4(<16 x i8> %vec, ptr %base, i64 %index, i32 %length) {
; CHECK-LABEL: test_vstrlr4:
-; CHECK: vstrlr %v24, %r4, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r2, %r3
+; CHECK-NEXT: vstrlr %v24, %r4, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 %index
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr)
ret void
@@ -174,8 +197,9 @@ define void @test_vstrlr4(<16 x i8> %vec, ptr %base, i64 %index, i32 %length) {
; VSTRL with the lowest in-range displacement.
define void @test_vstrl1(<16 x i8> %vec, ptr %ptr) {
; CHECK-LABEL: test_vstrl1:
-; CHECK: vstrl %v24, 0(%r2), 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrl %v24, 0(%r2), 8
+; CHECK-NEXT: br %r14
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr)
ret void
}
@@ -183,8 +207,9 @@ define void @test_vstrl1(<16 x i8> %vec, ptr %ptr) {
; VSTRL with the highest in-range displacement.
define void @test_vstrl2(<16 x i8> %vec, ptr %base) {
; CHECK-LABEL: test_vstrl2:
-; CHECK: vstrl %v24, 4095(%r2), 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrl %v24, 4095(%r2), 8
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4095
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr)
ret void
@@ -193,8 +218,10 @@ define void @test_vstrl2(<16 x i8> %vec, ptr %base) {
; VSTRL with an out-of-range displacement.
define void @test_vstrl3(<16 x i8> %vec, ptr %base) {
; CHECK-LABEL: test_vstrl3:
-; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstrl %v24, 0(%r2), 8
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 4096
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr)
ret void
@@ -203,8 +230,10 @@ define void @test_vstrl3(<16 x i8> %vec, ptr %base) {
; Check that VSTRL doesn't allow an index.
define void @test_vstrl4(<16 x i8> %vec, ptr %base, i64 %index) {
; CHECK-LABEL: test_vstrl4:
-; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agr %r2, %r3
+; CHECK-NEXT: vstrl %v24, 0(%r2), 8
+; CHECK-NEXT: br %r14
%ptr = getelementptr i8, ptr %base, i64 %index
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr)
ret void
@@ -213,8 +242,9 @@ define void @test_vstrl4(<16 x i8> %vec, ptr %base, i64 %index) {
; VSTRL with length >= 15 should become VST.
define void @test_vstrl5(<16 x i8> %vec, ptr %ptr) {
; CHECK-LABEL: test_vstrl5:
-; CHECK: vst %v24, 0({{%r[1-5]}})
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vst %v24, 0(%r2), 3
+; CHECK-NEXT: br %r14
call void @llvm.s390.vstrl(<16 x i8> %vec, i32 15, ptr %ptr)
ret void
}
@@ -222,10 +252,11 @@ define void @test_vstrl5(<16 x i8> %vec, ptr %ptr) {
; VFCESBS with no processing of the result.
define i32 @test_vfcesbs(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfcesbs:
-; CHECK: vfcesbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcesbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -235,10 +266,11 @@ define i32 @test_vfcesbs(<4 x float> %a, <4 x float> %b) {
; VFCESBS, returning 1 if any elements are equal (CC != 3).
define i32 @test_vfcesbs_any_bool(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfcesbs_any_bool:
-; CHECK: vfcesbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochile %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcesbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochile %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -249,13 +281,14 @@ define i32 @test_vfcesbs_any_bool(<4 x float> %a, <4 x float> %b) {
; VFCESBS, storing to %ptr if any elements are equal.
define <4 x i32> @test_vfcesbs_any_store(<4 x float> %a, <4 x float> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vfcesbs_any_store:
-; CHECK-NOT: %r
-; CHECK: vfcesbs %v24, %v24, %v26
-; CHECK-NEXT: {{bor|bnler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcesbs %v24, %v24, %v26
+; CHECK-NEXT: bor %r14
+; CHECK-NEXT: .LBB23_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -274,10 +307,11 @@ exit:
; VFCHSBS with no processing of the result.
define i32 @test_vfchsbs(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfchsbs:
-; CHECK: vfchsbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchsbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -287,10 +321,11 @@ define i32 @test_vfchsbs(<4 x float> %a, <4 x float> %b) {
; VFCHSBS, returning 1 if not all elements are higher.
define i32 @test_vfchsbs_notall_bool(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfchsbs_notall_bool:
-; CHECK: vfchsbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochinhe %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchsbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochinhe %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -301,13 +336,14 @@ define i32 @test_vfchsbs_notall_bool(<4 x float> %a, <4 x float> %b) {
; VFCHSBS, storing to %ptr if not all elements are higher.
define <4 x i32> @test_vfchsbs_notall_store(<4 x float> %a, <4 x float> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vfchsbs_notall_store:
-; CHECK-NOT: %r
-; CHECK: vfchsbs %v24, %v24, %v26
-; CHECK-NEXT: {{bher|ber}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchsbs %v24, %v24, %v26
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB26_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -326,10 +362,11 @@ exit:
; VFCHESBS with no processing of the result.
define i32 @test_vfchesbs(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfchesbs:
-; CHECK: vfchesbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchesbs %v0, %v24, %v26
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -339,10 +376,11 @@ define i32 @test_vfchesbs(<4 x float> %a, <4 x float> %b) {
; VFCHESBS, returning 1 if neither element is higher or equal.
define i32 @test_vfchesbs_none_bool(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfchesbs_none_bool:
-; CHECK: vfchesbs {{%v[0-9]+}}, %v24, %v26
-; CHECK: lhi %r2, 0
-; CHECK: lochio %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchesbs %v0, %v24, %v26
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochio %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 1
@@ -353,13 +391,14 @@ define i32 @test_vfchesbs_none_bool(<4 x float> %a, <4 x float> %b) {
; VFCHESBS, storing to %ptr if neither element is higher or equal.
define <4 x i32> @test_vfchesbs_none_store(<4 x float> %a, <4 x float> %b,
- ptr %ptr) {
; CHECK-LABEL: test_vfchesbs_none_store:
-; CHECK-NOT: %r
-; CHECK: vfchesbs %v24, %v24, %v26
-; CHECK-NEXT: {{bnor|bler}} %r14
-; CHECK: mvhi 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfchesbs %v24, %v24, %v26
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB29_1: # %store
+; CHECK-NEXT: mvhi 0(%r2), 0
+; CHECK-NEXT: br %r14
+ ptr %ptr) {
%call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a,
<4 x float> %b)
%res = extractvalue {<4 x i32>, i32} %call, 0
@@ -378,10 +417,11 @@ exit:
; VFTCISB with the lowest useful class selector and no processing of the result.
define i32 @test_vftcisb(<4 x float> %a) {
; CHECK-LABEL: test_vftcisb:
-; CHECK: vftcisb {{%v[0-9]+}}, %v24, 1
-; CHECK: ipm %r2
-; CHECK: srl %r2, 28
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vftcisb %v0, %v24, 1
+; CHECK-NEXT: ipm %r2
+; CHECK-NEXT: srl %r2, 28
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 1)
%res = extractvalue {<4 x i32>, i32} %call, 1
ret i32 %res
@@ -391,10 +431,11 @@ define i32 @test_vftcisb(<4 x float> %a) {
; have the right class (CC == 0).
define i32 @test_vftcisb_all_bool(<4 x float> %a) {
; CHECK-LABEL: test_vftcisb_all_bool:
-; CHECK: vftcisb {{%v[0-9]+}}, %v24, 4094
-; CHECK: lhi %r2, 0
-; CHECK: lochie %r2, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vftcisb %v0, %v24, 4094
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochie %r2, 1
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 4094)
%res = extractvalue {<4 x i32>, i32} %call, 1
%cmp = icmp eq i32 %res, 0
@@ -405,8 +446,9 @@ define i32 @test_vftcisb_all_bool(<4 x float> %a) {
; VFISB with a rounding mode not usable via standard intrinsics.
define <4 x float> @test_vfisb_0_4(<4 x float> %a) {
; CHECK-LABEL: test_vfisb_0_4:
-; CHECK: vfisb %v24, %v24, 0, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfisb %v24, %v24, 0, 4
+; CHECK-NEXT: br %r14
%res = call <4 x float> @llvm.s390.vfisb(<4 x float> %a, i32 0, i32 4)
ret <4 x float> %res
}
@@ -414,8 +456,9 @@ define <4 x float> @test_vfisb_0_4(<4 x float> %a) {
; VFISB with IEEE-inexact exception suppressed.
define <4 x float> @test_vfisb_4_0(<4 x float> %a) {
; CHECK-LABEL: test_vfisb_4_0:
-; CHECK: vfisb %v24, %v24, 4, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfisb %v24, %v24, 4, 0
+; CHECK-NEXT: br %r14
%res = call <4 x float> @llvm.s390.vfisb(<4 x float> %a, i32 4, i32 0)
ret <4 x float> %res
}
@@ -423,8 +466,9 @@ define <4 x float> @test_vfisb_4_0(<4 x float> %a) {
; VFMAXDB.
define <2 x double> @test_vfmaxdb(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfmaxdb:
-; CHECK: vfmaxdb %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmaxdb %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <2 x double> @llvm.s390.vfmaxdb(<2 x double> %a, <2 x double> %b, i32 4)
ret <2 x double> %res
}
@@ -432,8 +476,9 @@ define <2 x double> @test_vfmaxdb(<2 x double> %a, <2 x double> %b) {
; VFMINDB.
define <2 x double> @test_vfmindb(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_vfmindb:
-; CHECK: vfmindb %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmindb %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <2 x double> @llvm.s390.vfmindb(<2 x double> %a, <2 x double> %b, i32 4)
ret <2 x double> %res
}
@@ -441,8 +486,9 @@ define <2 x double> @test_vfmindb(<2 x double> %a, <2 x double> %b) {
; VFMAXSB.
define <4 x float> @test_vfmaxsb(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfmaxsb:
-; CHECK: vfmaxsb %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfmaxsb %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <4 x float> @llvm.s390.vfmaxsb(<4 x float> %a, <4 x float> %b, i32 4)
ret <4 x float> %res
}
@@ -450,8 +496,9 @@ define <4 x float> @test_vfmaxsb(<4 x float> %a, <4 x float> %b) {
; VFMINSB.
define <4 x float> @test_vfminsb(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vfminsb:
-; CHECK: vfminsb %v24, %v24, %v26, 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfminsb %v24, %v24, %v26, 4
+; CHECK-NEXT: br %r14
%res = call <4 x float> @llvm.s390.vfminsb(<4 x float> %a, <4 x float> %b, i32 4)
ret <4 x float> %res
}
diff --git a/llvm/test/CodeGen/SystemZ/vec-intrinsics-03.ll b/llvm/test/CodeGen/SystemZ/vec-intrinsics-03.ll
index 1ae53e8e1cf73..2788362593b59 100644
--- a/llvm/test/CodeGen/SystemZ/vec-intrinsics-03.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-intrinsics-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector intrinsics added with z15.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -16,8 +17,9 @@ declare {<16 x i8>, i32} @llvm.s390.vstrszf(<4 x i32>, <4 x i32>, <16 x i8>)
; VSLD with the minimum useful value.
define <16 x i8> @test_vsld_1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsld_1:
-; CHECK: vsld %v24, %v24, %v26, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsld %v24, %v24, %v26, 1
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 1)
ret <16 x i8> %res
}
@@ -25,8 +27,9 @@ define <16 x i8> @test_vsld_1(<16 x i8> %a, <16 x i8> %b) {
; VSLD with the maximum value.
define <16 x i8> @test_vsld_7(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsld_7:
-; CHECK: vsld %v24, %v24, %v26, 7
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsld %v24, %v24, %v26, 7
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 7)
ret <16 x i8> %res
}
@@ -34,8 +37,9 @@ define <16 x i8> @test_vsld_7(<16 x i8> %a, <16 x i8> %b) {
; VSRD with the minimum useful value.
define <16 x i8> @test_vsrd_1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsrd_1:
-; CHECK: vsrd %v24, %v24, %v26, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsrd %v24, %v24, %v26, 1
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 1)
ret <16 x i8> %res
}
@@ -43,8 +47,9 @@ define <16 x i8> @test_vsrd_1(<16 x i8> %a, <16 x i8> %b) {
; VSRD with the maximum value.
define <16 x i8> @test_vsrd_7(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vsrd_7:
-; CHECK: vsrd %v24, %v24, %v26, 7
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsrd %v24, %v24, %v26, 7
+; CHECK-NEXT: br %r14
%res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 7)
ret <16 x i8> %res
}
@@ -52,13 +57,14 @@ define <16 x i8> @test_vsrd_7(<16 x i8> %a, <16 x i8> %b) {
; VSTRSB.
define <16 x i8> @test_vstrsb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrsb:
-; CHECK: vstrsb %v24, %v24, %v26, %v28, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrsb %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrsb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -69,13 +75,14 @@ define <16 x i8> @test_vstrsb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
; VSTRSH.
define <16 x i8> @test_vstrsh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrsh:
-; CHECK: vstrsh %v24, %v24, %v26, %v28, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrsh %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrsh(<8 x i16> %a, <8 x i16> %b,
<16 x i8> %c)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -86,13 +93,14 @@ define <16 x i8> @test_vstrsh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c,
; VSTRSFS.
define <16 x i8> @test_vstrsf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrsf:
-; CHECK: vstrsf %v24, %v24, %v26, %v28, 0
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrsf %v24, %v24, %v26, %v28, 0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrsf(<4 x i32> %a, <4 x i32> %b,
<16 x i8> %c)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -103,13 +111,14 @@ define <16 x i8> @test_vstrsf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c,
; VSTRSZB.
define <16 x i8> @test_vstrszb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrszb:
-; CHECK: vstrszb %v24, %v24, %v26, %v28
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrszb %v24, %v24, %v26, %v28
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrszb(<16 x i8> %a, <16 x i8> %b,
<16 x i8> %c)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -120,13 +129,14 @@ define <16 x i8> @test_vstrszb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
; VSTRSZH.
define <16 x i8> @test_vstrszh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrszh:
-; CHECK: vstrszh %v24, %v24, %v26, %v28
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrszh %v24, %v24, %v26, %v28
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrszh(<8 x i16> %a, <8 x i16> %b,
<16 x i8> %c)
%res = extractvalue {<16 x i8>, i32} %call, 0
@@ -137,13 +147,14 @@ define <16 x i8> @test_vstrszh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c,
; VSTRSZF.
define <16 x i8> @test_vstrszf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c,
- ptr %ccptr) {
; CHECK-LABEL: test_vstrszf:
-; CHECK: vstrszf %v24, %v24, %v26, %v28
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: srl [[REG]], 28
-; CHECK: st [[REG]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstrszf %v24, %v24, %v26, %v28
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: srl %r0, 28
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+ ptr %ccptr) {
%call = call {<16 x i8>, i32} @llvm.s390.vstrszf(<4 x i32> %a, <4 x i32> %b,
<16 x i8> %c)
%res = extractvalue {<16 x i8>, i32} %call, 0
diff --git a/llvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll b/llvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
index 351a981f7018b..423346e9bd43a 100644
--- a/llvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector intrinsics added with z16.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s
@@ -11,8 +12,9 @@ declare <8 x i16> @llvm.s390.vcnf(<8 x i16>, i32)
; VCLFNH.
define <4 x float> @test_vclfnhs(<8 x i16> %a) {
; CHECK-LABEL: test_vclfnhs:
-; CHECK: vclfnh %v24, %v24, 2, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclfnh %v24, %v24, 2, 0
+; CHECK-NEXT: br %r14
%res = call <4 x float> @llvm.s390.vclfnhs(<8 x i16> %a, i32 0)
ret <4 x float> %res
}
@@ -20,8 +22,9 @@ define <4 x float> @test_vclfnhs(<8 x i16> %a) {
; VCLFNL.
define <4 x float> @test_vclfnls(<8 x i16> %a) {
; CHECK-LABEL: test_vclfnls:
-; CHECK: vclfnl %v24, %v24, 2, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclfnl %v24, %v24, 2, 0
+; CHECK-NEXT: br %r14
%res = call <4 x float> @llvm.s390.vclfnls(<8 x i16> %a, i32 0)
ret <4 x float> %res
}
@@ -29,8 +32,9 @@ define <4 x float> @test_vclfnls(<8 x i16> %a) {
; VCRNF.
define <8 x i16> @test_vcrnfs(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcrnfs:
-; CHECK: vcrnf %v24, %v24, %v26, 0, 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcrnf %v24, %v24, %v26, 0, 2
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vcrnfs(<4 x float> %a, <4 x float> %b, i32 0)
ret <8 x i16> %res
}
@@ -38,8 +42,9 @@ define <8 x i16> @test_vcrnfs(<4 x float> %a, <4 x float> %b) {
; VCFN.
define <8 x i16> @test_vcfn(<8 x i16> %a) {
; CHECK-LABEL: test_vcfn:
-; CHECK: vcfn %v24, %v24, 1, 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcfn %v24, %v24, 1, 0
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vcfn(<8 x i16> %a, i32 0)
ret <8 x i16> %res
}
@@ -47,8 +52,9 @@ define <8 x i16> @test_vcfn(<8 x i16> %a) {
; VCNF.
define <8 x i16> @test_vcnf(<8 x i16> %a) {
; CHECK-LABEL: test_vcnf:
-; CHECK: vcnf %v24, %v24, 0, 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vcnf %v24, %v24, 0, 1
+; CHECK-NEXT: br %r14
%res = call <8 x i16> @llvm.s390.vcnf(<8 x i16> %a, i32 0)
ret <8 x i16> %res
}
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