[llvm] Subject: [PATCH] [AArch64ISelLowering] Optimize rounding shift and saturation truncation (PR #74325)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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git-clang-format --diff bc8cff1d7fb2069aa3f7333e25642f2571049af1 b2453bda5759c28558f60cf3ed309e2776210914 -- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 17da58f892..d0d35017a3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -111,10 +111,10 @@ STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
 STATISTIC(NumOptimizedImms, "Number of times immediates were optimized");
 
-static cl::opt<bool> EnableAArch64RoundingOpt(
-    "aarch64-optimize-rounding", cl::Hidden,
-    cl::desc("Enable AArch64 rounding optimization"),
-    cl::init(true));
+static cl::opt<bool>
+    EnableAArch64RoundingOpt("aarch64-optimize-rounding", cl::Hidden,
+                             cl::desc("Enable AArch64 rounding optimization"),
+                             cl::init(true));
 
 static cl::opt<bool> EnableAArch64RoundingSatNarrowOpt(
     "aarch64-optimize-rounding-saturation", cl::Hidden,
@@ -18620,13 +18620,13 @@ static SDValue performConcatVectorsCombine(SDNode *N,
        N1.isUndef())) {
     if (N0.getOpcode() == AArch64ISD::URSHR_I) {
       SDValue X = N0.getOperand(0);
-      SDValue Y = N1.isUndef() ? DAG.getUNDEF(X.getValueType())
-                             : N1.getOperand(0);
+      SDValue Y =
+          N1.isUndef() ? DAG.getUNDEF(X.getValueType()) : N1.getOperand(0);
       EVT BVT =
-        X.getValueType().getDoubleNumVectorElementsVT(*DCI.DAG.getContext());
+          X.getValueType().getDoubleNumVectorElementsVT(*DCI.DAG.getContext());
       SDValue CC = DAG.getNode(ISD::CONCAT_VECTORS, dl, BVT, X, Y);
       SDValue Shr =
-        DAG.getNode(AArch64ISD::URSHR_I, dl, BVT, CC, N0.getOperand(1));
+          DAG.getNode(AArch64ISD::URSHR_I, dl, BVT, CC, N0.getOperand(1));
       return Shr;
     }
     SDValue X = N0.getOperand(0).getOperand(0);
@@ -19384,8 +19384,7 @@ static SDValue performBuildVectorCombine(SDNode *N,
   return SDValue();
 }
 
-static SDValue performTruncateCombine(SDNode *N,
-                             SelectionDAG &DAG) {
+static SDValue performTruncateCombine(SDNode *N, SelectionDAG &DAG) {
   EVT VT = N->getValueType(0);
   bool HasNeon =
       static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasNEON();

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https://github.com/llvm/llvm-project/pull/74325