[llvm] 725656b - [M68k] Emit RTE for interrupt handler. (#72787)

[via llvm-commits]

Author: Sheng
Date: 2023-12-04T15:11:00+08:00
New Revision: 725656bdd885483c39f482a01ea25d67acf39c46

URL: https://github.com/llvm/llvm-project/commit/725656bdd885483c39f482a01ea25d67acf39c46
DIFF: https://github.com/llvm/llvm-project/commit/725656bdd885483c39f482a01ea25d67acf39c46.diff

LOG: [M68k] Emit RTE for interrupt handler. (#72787)

Fixes #64833

Added: 
    llvm/test/CodeGen/M68k/CConv/rte.ll

Modified: 
    llvm/lib/Target/M68k/M68kExpandPseudo.cpp
    llvm/lib/Target/M68k/M68kInstrControl.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
index 13268d754a9dd..7bd3821077737 100644
--- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
+++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
@@ -252,12 +252,11 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
     return true;
   }
   case M68k::RET: {
-    // Adjust stack to erase error code
-    int64_t StackAdj = MBBI->getOperand(0).getImm();
-    MachineInstrBuilder MIB;
-
-    if (StackAdj == 0) {
-      MIB = BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
+    if (MBB.getParent()->getFunction().getCallingConv() ==
+        CallingConv::M68k_INTR) {
+      BuildMI(MBB, MBBI, DL, TII->get(M68k::RTE));
+    } else if (int64_t StackAdj = MBBI->getOperand(0).getImm(); StackAdj == 0) {
+      BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
     } else {
       // Copy return address from stack to a free address(A0 or A1) register
       // TODO check if pseudo expand uses free address register

diff  --git a/llvm/lib/Target/M68k/M68kInstrControl.td b/llvm/lib/Target/M68k/M68kInstrControl.td
index 225f932f33166..6e116d7cfe401 100644
--- a/llvm/lib/Target/M68k/M68kInstrControl.td
+++ b/llvm/lib/Target/M68k/M68kInstrControl.td
@@ -327,6 +327,10 @@ def RTS : MxInst<(outs), (ins), "rts", []> {
   let Inst = (descend 0b0100, 0b1110, 0b0111, 0b0101);
 }
 
+def RTE: MxInst<(outs), (ins), "rte", []> {
+  let Inst = (descend 0b0100, 0b1110, 0b0111, 0b0011);
+}
+
 let isCodeGenOnly = 1 in
 def RET : MxPseudo<(outs), (ins i32imm:$adj, variable_ops),
                    [(MxRet timm:$adj)]>;

diff  --git a/llvm/test/CodeGen/M68k/CConv/rte.ll b/llvm/test/CodeGen/M68k/CConv/rte.ll
new file mode 100644
index 0000000000000..da7eb1bdc70e7
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/CConv/rte.ll
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple m68k -o - %s | FileCheck %s
+
+define cc101 void @interrupt_handler() {
+; CHECK-LABEL: interrupt_handler:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    rte
+entry:
+  ret void
+}