[llvm] [RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (PR #73969)

[Wang Pengcheng via llvm-commits]

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@@ -37,13 +37,13 @@ vle64.v v1, (a1)
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      26
-# CHECK-NEXT: Total Cycles:      3523
+# CHECK-NEXT: Total Cycles:      3546
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wangpc-pp wrote:

The `Total Cycles` increases and `Block RThroughput` also increases, but can I consider this as what we want? As we need more cycles to occupy `SiFive7VCQ` but the resources can be better utilized. But the `Throughput` seems to be decreased in llvm-mca's simulation.

https://github.com/llvm/llvm-project/pull/73969