[llvm] [RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (PR #73969)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 3 19:19:57 PST 2023
================
@@ -37,13 +37,13 @@ vle64.v v1, (a1)
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 26
-# CHECK-NEXT: Total Cycles: 3523
+# CHECK-NEXT: Total Cycles: 3546
----------------
wangpc-pp wrote:
The `Total Cycles` increases and `Block RThroughput` also increases, but can I consider this as what we want? As we need more cycles to occupy `SiFive7VCQ` but the resources can be better utilized. But the `Throughput` seems to be decreased in llvm-mca's simulation.
https://github.com/llvm/llvm-project/pull/73969
More information about the llvm-commits
mailing list