[llvm] [RISCV] Rematerialize load (PR #73924)

[Niwin Anto via llvm-commits]

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@@ -626,7 +626,7 @@ def BGE  : BranchCC_rri<0b101, "bge">;
 def BLTU : BranchCC_rri<0b110, "bltu">;
 def BGEU : BranchCC_rri<0b111, "bgeu">;
 
-let IsSignExtendingOpW = 1 in {
+let IsSignExtendingOpW = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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niwinanto wrote:

@jrtc27 Yeah, it doesn't make sense to `isAsCheapAsAMove` to be true for loads. However, if I wanted to achieve the usecase, then I need to force the `RegisterCoalescer::reMaterializeTrivialDef` to rematerialize load even for not asCheapAsMove instructions. But it can affect other targets as well, I am not sure its side effects. May be I can introduce a target hook in TII(eg:allowAggressiveRemat) so targets can decide. But in general, I don't see a problem for this remat. What do you think?

https://github.com/llvm/llvm-project/pull/73924