https://github.com/topperc created https://github.com/llvm/llvm-project/pull/74156
None
>From 0427b3bbdac3d67c8ddefce46bd95c3da643c31c Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 1 Dec 2023 15:13:30 -0800
Subject: [PATCH 1/2] [RISCV] Add test case showing that removal of W suffixes
doesn't work with DBG_VALUE uses. NFC
---
.../CodeGen/RISCV/sextw-removal-debug.mir | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir b/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
new file mode 100644
index 000000000000000..c917abbd8f211ea
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -o - | FileCheck %s
+
+--- |
+ define void @foo(i32 signext %a, i32 signext %b, ptr %c) !dbg !5 {
+ entry:
+ %add = add nsw i32 %b, %a, !dbg !11
+ tail call void @llvm.dbg.value(metadata i32 %add, metadata !9, metadata !DIExpression()), !dbg !11
+ store i32 %add, ptr %c, align 4, !dbg !12
+ ret void, !dbg !13
+ }
+
+ declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+
+ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.debugify = !{!2, !3}
+ !llvm.module.flags = !{!4}
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+ !1 = !DIFile(filename: "test.ll", directory: "/")
+ !2 = !{i32 3}
+ !3 = !{i32 1}
+ !4 = !{i32 2, !"Debug Info Version", i32 3}
+ !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
+ !6 = !DISubroutineType(types: !7)
+ !7 = !{}
+ !8 = !{!9}
+ !9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10)
+ !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
+ !11 = !DILocation(line: 1, column: 1, scope: !5)
+ !12 = !DILocation(line: 2, column: 1, scope: !5)
+ !13 = !DILocation(line: 3, column: 1, scope: !5)
+
+...
+---
+name: foo
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; CHECK-LABEL: name: foo
+ ; CHECK: liveins: $x10, $x11, $x12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]], debug-location !11
+ ; CHECK-NEXT: DBG_VALUE [[ADDW]], $noreg, !9, !DIExpression(), debug-location !11
+ ; CHECK-NEXT: SW killed [[ADDW]], [[COPY]], 0, debug-location !12 :: (store (s32) into %ir.c)
+ ; CHECK-NEXT: PseudoRET debug-location !13
+ %2:gpr = COPY $x12
+ %1:gpr = COPY $x11
+ %0:gpr = COPY $x10
+ %3:gpr = ADDW %1, %0, debug-location !11
+ DBG_VALUE %3, $noreg, !9, !DIExpression(), debug-location !11
+ SW killed %3, %2, 0, debug-location !12 :: (store (s32) into %ir.c)
+ PseudoRET debug-location !13
+
+...
>From b7517cbcc34b26884bce11f622dc34fb39207d5e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 1 Dec 2023 15:14:57 -0800
Subject: [PATCH 2/2] [RISCV] Ignore debug instructions in hasAllNBitUsers in
RISCVOptWInstrs.
---
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 2 +-
llvm/test/CodeGen/RISCV/sextw-removal-debug.mir | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 9101dd67fb0d3d1..b667a2b7a11bac5 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -128,7 +128,7 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
if (MI->getNumExplicitDefs() != 1)
return false;
- for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
+ for (auto &UserOp : MRI.use_nodbg_operands(MI->getOperand(0).getReg())) {
const MachineInstr *UserMI = UserOp.getParent();
unsigned OpIdx = UserOp.getOperandNo();
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir b/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
index c917abbd8f211ea..f8d6d4b13846e28 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
+++ b/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir
@@ -47,9 +47,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]], debug-location !11
- ; CHECK-NEXT: DBG_VALUE [[ADDW]], $noreg, !9, !DIExpression(), debug-location !11
- ; CHECK-NEXT: SW killed [[ADDW]], [[COPY]], 0, debug-location !12 :: (store (s32) into %ir.c)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY2]], debug-location !11
+ ; CHECK-NEXT: DBG_VALUE [[ADD]], $noreg, !9, !DIExpression(), debug-location !11
+ ; CHECK-NEXT: SW killed [[ADD]], [[COPY]], 0, debug-location !12 :: (store (s32) into %ir.c)
; CHECK-NEXT: PseudoRET debug-location !13
%2:gpr = COPY $x12
%1:gpr = COPY $x11