[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Michael Maitland via llvm-commits]

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@@ -240,6 +254,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
                                           : RISCV::GPRB32Idx];
 
+  unsigned VRBSize = getMaximumSize(RISCV::VRBRegBankID);
+  const ValueMapping *VRBValueMapping =
+      &RISCV::ValueMappings[VRBSize == 64 ? RISCV::VRB64Idx : RISCV::VRB32Idx];
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michaelmaitland wrote:

It looks like in `build/lib/Target/RISCV/RISCVGenRegisterBank.inc` that the `Sizes` array has 512 for both RV32 and RV64 for VRB.

https://github.com/llvm/llvm-project/pull/74114