[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 1 09:37:37 PST 2023


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff ea4eb691f4955e3b784ebf9bc94a47186838c6f2 0a2f5de606362f477d54dcd9e7f43e888e4b5871 -- llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index f3be5ba74b..3531d5dc30 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -25,12 +25,8 @@ namespace llvm {
 namespace RISCV {
 
 const RegisterBankInfo::PartialMapping PartMappings[] = {
-    {0, 32, GPRBRegBank},
-    {0, 64, GPRBRegBank},
-    {0, 32, FPRBRegBank},
-    {0, 64, FPRBRegBank},
-    {0, 32, VRBRegBank},
-    {0, 64, VRBRegBank},
+    {0, 32, GPRBRegBank}, {0, 64, GPRBRegBank}, {0, 32, FPRBRegBank},
+    {0, 64, FPRBRegBank}, {0, 32, VRBRegBank},  {0, 64, VRBRegBank},
 };
 
 enum PartialMappingIdx {

``````````

</details>


https://github.com/llvm/llvm-project/pull/74114


More information about the llvm-commits mailing list