[llvm] [RISCV] Rework IDiv and FDiv pipes on SiFive7 (PR #73970)

[Wang Pengcheng via llvm-commits]

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@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {
 def SiFive7PipeA       : ProcResource<1>;
 def SiFive7PipeB       : ProcResource<1>;
+def SiFive7IDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
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wangpc-pp wrote:

IIUC, the bahavior is different. If there is no `Super`, `SiFive7PipeB` will be released after 1 cycle; if `Super` is specified, `SiFive7PipeB` will still be occupied after 1 cycle as SiFive7IDiv implictly use it. I don't the details about the real pipeline, is it desired?

https://github.com/llvm/llvm-project/pull/73970