[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Matt Arsenault via llvm-commits]

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@@ -29,6 +29,39 @@
 
 using namespace llvm;
 
+static bool CC_AMDGPU_Custom_I1(unsigned ValNo, MVT ValVT, MVT LocVT,
+                                CCValAssign::LocInfo LocInfo,
+                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
+  static bool IsWave64 = static_cast<const GCNSubtarget &>(
+                             State.getMachineFunction().getSubtarget())
+                             .isWave64();
+
+  static const MCPhysReg I1RegList1[] = {
+      AMDGPU::SGPR0_SGPR1,   AMDGPU::SGPR2_SGPR3,   AMDGPU::SGPR4_SGPR5,
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arsenm wrote:

Do we want to only pass in even aligned registers? We could also include all the aliasing odd-based cases

https://github.com/llvm/llvm-project/pull/72461