[llvm] [AArch64][SME] Remove implicit-def's on smstart (PR #69012)

[Jon Roelofs via llvm-commits]

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@@ -7283,6 +7283,22 @@ static bool checkZExtBool(SDValue Arg, const SelectionDAG &DAG) {
   return ZExtBool;
 }
 
+void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
+                                                          SDNode *Node) const {
+  // Live-in physreg copies that are glued to SMSTART are applied as
+  // implicit-def's in the InstrEmitter. Here we remove them, allowing the
+  // register allocator to pass call args in callee saved regs, without extra
+  // copies to avoid these fake clobbers of actually-preserved GPRs.
+  if (MI.getOpcode() == AArch64::MSRpstatesvcrImm1 ||
+      MI.getOpcode() == AArch64::MSRpstatePseudo)
+    for (unsigned I = MI.getNumOperands() - 1; I > 0; --I)
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jroelofs wrote:

This appears to be the common pattern for removing operands. Starting from the end means marginally ness shuffling of not-removed operands, too.

https://github.com/llvm/llvm-project/pull/69012