[llvm] 306e13e - [RISCV][GISel] Remove unnecessary Observer notifications from legalizeVAStart.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-30T09:53:37-08:00
New Revision: 306e13e499e45c8a2b24bd00937688fade8ad41e

URL: https://github.com/llvm/llvm-project/commit/306e13e499e45c8a2b24bd00937688fade8ad41e
DIFF: https://github.com/llvm/llvm-project/commit/306e13e499e45c8a2b24bd00937688fade8ad41e.diff

LOG: [RISCV][GISel] Remove unnecessary Observer notifications from legalizeVAStart.

MIRBuilder already tells the observer when an instruction is created.

No other legalizer code on any target tells the observer when it
erases the instruction it was asked to legalize.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 9564ed9c41874a7..609c26c8e16627d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -331,8 +331,7 @@ bool RISCVLegalizerInfo::legalizeShlAshrLshr(
 }
 
 bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI,
-                                         MachineIRBuilder &MIRBuilder,
-                                         GISelChangeObserver &Observer) const {
+                                         MachineIRBuilder &MIRBuilder) const {
   // Stores the address of the VarArgsFrameIndex slot into the memory location
   assert(MI.getOpcode() == TargetOpcode::G_VASTART);
   MachineFunction *MF = MI.getParent()->getParent();
@@ -341,10 +340,8 @@ bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI,
   LLT AddrTy = MIRBuilder.getMRI()->getType(MI.getOperand(0).getReg());
   auto FINAddr = MIRBuilder.buildFrameIndex(AddrTy, FI);
   assert(MI.hasOneMemOperand());
-  MachineInstr *LoweredMI = MIRBuilder.buildStore(
-      MI.getOperand(0).getReg(), FINAddr, *MI.memoperands()[0]);
-  Observer.createdInstr(*LoweredMI);
-  Observer.erasingInstr(MI);
+  MIRBuilder.buildStore(MI.getOperand(0).getReg(), FINAddr,
+                        *MI.memoperands()[0]);
   MI.eraseFromParent();
   return true;
 }
@@ -390,7 +387,7 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
     return true;
   }
   case TargetOpcode::G_VASTART:
-    return legalizeVAStart(MI, MIRBuilder, Observer);
+    return legalizeVAStart(MI, MIRBuilder);
   }
 
   llvm_unreachable("expected switch to return");

diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index c0e6088ac5c193b..246ea90dcd74903 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -36,8 +36,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
   bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
                            GISelChangeObserver &Observer) const;
 
-  bool legalizeVAStart(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
-                       GISelChangeObserver &Observer) const;
+  bool legalizeVAStart(MachineInstr &MI, MachineIRBuilder &MIRBuilder) const;
 };
 } // end namespace llvm
 #endif