[llvm] 6976dac - [RISCV][GISEL] regbankselect and instruction-select for G_IMPLICIT_DEF (#73060)
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llvm-commits at lists.llvm.org
Thu Nov 30 08:38:08 PST 2023
Author: Michael Maitland
Date: 2023-11-30T11:38:02-05:00
New Revision: 6976dac09db6dab3ef9eb68f1d19b70aa2847773
URL: https://github.com/llvm/llvm-project/commit/6976dac09db6dab3ef9eb68f1d19b70aa2847773
DIFF: https://github.com/llvm/llvm-project/commit/6976dac09db6dab3ef9eb68f1d19b70aa2847773.diff
LOG: [RISCV][GISEL] regbankselect and instruction-select for G_IMPLICIT_DEF (#73060)
This is similar to the selection of G_IMPLICIT_DEF in AArch64.
Regbankselect may need to be improved in a future patch.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 9b4577dec87c570..6e5829ba93a7128 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -62,6 +62,8 @@ class RISCVInstructionSelector : public InstructionSelector {
// Custom selection methods
bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
+ bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB,
+ MachineRegisterInfo &MRI) const;
bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI, bool IsLocal = true,
@@ -623,6 +625,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
MI.eraseFromParent();
return true;
}
+ case TargetOpcode::G_IMPLICIT_DEF:
+ return selectImplicitDef(MI, MIB, MRI);
default:
return false;
}
@@ -736,6 +740,25 @@ bool RISCVInstructionSelector::selectCopy(MachineInstr &MI,
return true;
}
+bool RISCVInstructionSelector::selectImplicitDef(
+ MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
+
+ const Register DstReg = MI.getOperand(0).getReg();
+ const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(
+ MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI));
+
+ assert(DstRC &&
+ "Register class not available for LLT, register bank combination");
+
+ if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+ LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
+ << " operand\n");
+ }
+ MI.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
+ return true;
+}
+
bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm,
MachineIRBuilder &MIB) const {
MachineRegisterInfo &MRI = *MIB.getMRI();
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index b8fafa154ca9ca5..8f274f0417cac62 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -207,6 +207,14 @@ bool RISCVRegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
return hasFPConstraints(MI, MRI, TRI);
}
+bool RISCVRegisterBankInfo::anyUseOnlyUseFP(
+ Register Def, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const {
+ return any_of(
+ MRI.use_nodbg_instructions(Def),
+ [&](const MachineInstr &UseMI) { return onlyUsesFP(UseMI, MRI, TRI); });
+}
+
const RegisterBankInfo::InstructionMapping &
RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const unsigned Opc = MI.getOpcode();
@@ -277,6 +285,19 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
getFPValueMapping(Ty.getSizeInBits()),
NumOperands);
}
+ case TargetOpcode::G_IMPLICIT_DEF: {
+ Register Dst = MI.getOperand(0).getReg();
+ auto Mapping = GPRValueMapping;
+ // FIXME: May need to do a better job determining when to use FPRB.
+ // For example, the look through COPY case:
+ // %0:_(s32) = G_IMPLICIT_DEF
+ // %1:_(s32) = COPY %0
+ // $f10_d = COPY %1(s32)
+ if (anyUseOnlyUseFP(Dst, MRI, TRI))
+ Mapping = getFPValueMapping(MRI.getType(Dst).getSizeInBits());
+ return getInstructionMapping(DefaultMappingID, /*Cost=*/1, Mapping,
+ NumOperands);
+ }
}
SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
@@ -296,14 +317,11 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// Check if that load feeds fp instructions.
// In that case, we want the default mapping to be on FPR
// instead of blind map every scalar to GPR.
- if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
- [&](const MachineInstr &UseMI) {
- // If we have at least one direct use in a FP instruction,
- // assume this was a floating point load in the IR. If it was
- // not, we would have had a bitcast before reaching that
- // instruction.
- return onlyUsesFP(UseMI, MRI, TRI);
- }))
+ if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI))
+ // If we have at least one direct use in a FP instruction,
+ // assume this was a floating point load in the IR. If it was
+ // not, we would have had a bitcast before reaching that
+ // instruction.
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
break;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
index 7e460588f19dba1..abd0837395f665a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
@@ -48,6 +48,10 @@ class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const;
+ /// \returns true if any use of \p Def only user FPRs.
+ bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const;
+
/// \returns true if \p MI only defines FPRs.
bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir
new file mode 100644
index 000000000000000..5450ac736fe2600
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir
@@ -0,0 +1,59 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32F %s
+
+---
+name: implicit_def_gpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_gpr
+ ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+ ; RV32F-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]
+ ; RV32F-NEXT: $x10 = COPY [[ADD]]
+ %0:gprb(s32) = G_IMPLICIT_DEF
+ %1:gprb(s32) = G_ADD %0, %0
+ $x10 = COPY %1(s32)
+...
+---
+name: implicit_def_copy_gpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_copy_gpr
+ ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+ ; RV32F-NEXT: $x10 = COPY [[DEF]]
+ %0:gprb(s32) = G_IMPLICIT_DEF
+ %1:gprb(s32) = COPY %0(s32)
+ $x10 = COPY %1(s32)
+...
+
+---
+name: implicit_def_fpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_fpr
+ ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
+ ; RV32F-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[DEF]], [[DEF]], 7
+ ; RV32F-NEXT: $f10_f = COPY [[FADD_S]]
+ %0:fprb(s32) = G_IMPLICIT_DEF
+ %1:fprb(s32) = G_FADD %0, %0
+ $f10_f = COPY %1(s32)
+...
+---
+name: implicit_def_copy_fpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_copy_fpr
+ ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF
+ ; RV32F-NEXT: $f10_f = COPY [[DEF]]
+ %0:fprb(s32) = G_IMPLICIT_DEF
+ %1:fprb(s32) = COPY %0(s32)
+ $f10_f = COPY %1(s32)
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir
new file mode 100644
index 000000000000000..e0fc237a18535d8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir
@@ -0,0 +1,59 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV64D %s
+
+---
+name: implicit_def_gpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_gpr
+ ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+ ; RV64D-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]
+ ; RV64D-NEXT: $x10 = COPY [[ADD]]
+ %0:gprb(s64) = G_IMPLICIT_DEF
+ %1:gprb(s64) = G_ADD %0, %0
+ $x10 = COPY %1(s64)
+...
+---
+name: implicit_def_copy_gpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_copy_gpr
+ ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+ ; RV64D-NEXT: $x10 = COPY [[DEF]]
+ %0:gprb(s64) = G_IMPLICIT_DEF
+ %1:gprb(s64) = COPY %0(s64)
+ $x10 = COPY %1(s64)
+...
+
+---
+name: implicit_def_fpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_fpr
+ ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
+ ; RV64D-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[DEF]], [[DEF]], 7
+ ; RV64D-NEXT: $f10_d = COPY [[FADD_D]]
+ %0:fprb(s64) = G_IMPLICIT_DEF
+ %1:fprb(s64) = G_FADD %0, %0
+ $f10_d = COPY %1(s64)
+...
+---
+name: implicit_def_copy_fpr
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_copy_fpr
+ ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
+ ; RV64D-NEXT: $f10_d = COPY [[DEF]]
+ %0:fprb(s64) = G_IMPLICIT_DEF
+ %1:fprb(s64) = COPY %0(s64)
+ $f10_d = COPY %1(s64)
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
new file mode 100644
index 000000000000000..f084af59fdf4d51
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32F %s
+
+---
+name: implicit_def_gpr
+legalized: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_gpr
+ ; RV32F: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
+ ; RV32F-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[DEF]], [[DEF]]
+ ; RV32F-NEXT: $x10 = COPY [[ADD]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
+ %1:_(s32) = G_ADD %0, %0
+ $x10 = COPY %1(s32)
+...
+---
+name: implicit_def_copy_gpr
+legalized: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_copy_gpr
+ ; RV32F: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
+ ; RV32F-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[DEF]](s32)
+ ; RV32F-NEXT: $x10 = COPY [[COPY]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
+ %1:_(s32) = COPY %0(s32)
+ $x10 = COPY %1(s32)
+...
+
+---
+name: implicit_def_fpr
+legalized: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_fpr
+ ; RV32F: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF
+ ; RV32F-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[DEF]], [[DEF]]
+ ; RV32F-NEXT: $f10_f = COPY [[FADD]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
+ %1:_(s32) = G_FADD %0, %0
+ $f10_f = COPY %1(s32)
+...
+---
+name: implicit_def_copy_fpr
+legalized: true
+body: |
+ bb.0:
+ ; RV32F-LABEL: name: implicit_def_copy_fpr
+ ; RV32F: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF
+ ; RV32F-NEXT: $f10_f = COPY [[DEF]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
+ $f10_f = COPY %0(s32)
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
new file mode 100644
index 000000000000000..caece8b68ce0b28
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir
@@ -0,0 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV64D %s
+
+---
+name: implicit_def_gpr
+legalized: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_gpr
+ ; RV64D: [[DEF:%[0-9]+]]:gprb(s64) = G_IMPLICIT_DEF
+ ; RV64D-NEXT: [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[DEF]], [[DEF]]
+ ; RV64D-NEXT: $x10 = COPY [[ADD]](s64)
+ %0:_(s64) = G_IMPLICIT_DEF
+ %1:_(s64) = G_ADD %0, %0
+ $x10 = COPY %1(s64)
+...
+---
+name: implicit_def_copy_gpr
+legalized: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_copy_gpr
+ ; RV64D: [[DEF:%[0-9]+]]:gprb(s64) = G_IMPLICIT_DEF
+ ; RV64D-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY [[DEF]](s64)
+ ; RV64D-NEXT: $x10 = COPY [[COPY]](s64)
+ %0:_(s64) = G_IMPLICIT_DEF
+ %1:_(s64) = COPY %0(s64)
+ $x10 = COPY %1(s64)
+...
+
+---
+name: implicit_def_fpr
+legalized: true
+body: |
+ bb.0:
+ ; RV64D-LABEL: name: implicit_def_fpr
+ ; RV64D: [[DEF:%[0-9]+]]:fprb(s64) = G_IMPLICIT_DEF
+ ; RV64D-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[DEF]], [[DEF]]
+ ; RV64D-NEXT: $f10_d = COPY [[FADD]](s64)
+ %0:_(s64) = G_IMPLICIT_DEF
+ %1:_(s64) = G_FADD %0, %0
+ $f10_d = COPY %1(s64)
+...
+---
+name: implicit_def_copy_fpr
+legalized: true
+body: |
+ bb.0:
+ %0:_(s64) = G_IMPLICIT_DEF
+ $f10_d = COPY %0(s64)
+...
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