[llvm] 3f6a8e9 - [InstCombine] Switch to use FileCheck as UTC was favoured (NFC)

[Antonio Frighetto via llvm-commits]

Author: Antonio Frighetto
Date: 2023-11-30T14:14:21+01:00
New Revision: 3f6a8e9b18154accc78e620b843b3721c23703b1

URL: https://github.com/llvm/llvm-project/commit/3f6a8e9b18154accc78e620b843b3721c23703b1
DIFF: https://github.com/llvm/llvm-project/commit/3f6a8e9b18154accc78e620b843b3721c23703b1.diff

LOG: [InstCombine] Switch to use FileCheck as UTC was favoured (NFC)

FileCheck was previously missing while moving to UTC, as part of
regenerating other tests within InstCombine.

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/add3.ll
    llvm/test/Transforms/InstCombine/addnegneg.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/add3.ll b/llvm/test/Transforms/InstCombine/add3.ll
index 811173d11ff4195..ba9ce8e64438d2b 100644
--- a/llvm/test/Transforms/InstCombine/add3.ll
+++ b/llvm/test/Transforms/InstCombine/add3.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
-; RUN: opt < %s -passes=instcombine -S | grep inttoptr | count 2
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 ;; Target triple for gep raising case below.
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
@@ -7,6 +7,19 @@ target triple = "i686-apple-darwin8"
 
 ; PR1795
 define void @test2(i32 %.val24) {
+; CHECK-LABEL: define void @test2(
+; CHECK-SAME: i32 [[DOTVAL24:%.*]]) {
+; CHECK-NEXT:  EntryBlock:
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[DOTVAL24]], -12
+; CHECK-NEXT:    [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to ptr
+; CHECK-NEXT:    store i32 1, ptr [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[DOTVAL24]], -16
+; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr i32, ptr [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = tail call i32 @callee(i32 [[TMP5]])
+; CHECK-NEXT:    ret void
+;
 EntryBlock:
   add i32 %.val24, -12
   inttoptr i32 %0 to ptr

diff  --git a/llvm/test/Transforms/InstCombine/addnegneg.ll b/llvm/test/Transforms/InstCombine/addnegneg.ll
index aef93fe517afbe6..29a11e062855838 100644
--- a/llvm/test/Transforms/InstCombine/addnegneg.ll
+++ b/llvm/test/Transforms/InstCombine/addnegneg.ll
@@ -1,8 +1,15 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
-; RUN: opt < %s -passes=instcombine -S | grep " sub " | count 1
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 ; PR2047
 
 define i32 @l(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK-LABEL: define i32 @l(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[C]], [[B]]
+; CHECK-NEXT:    [[SUB6:%.*]] = sub i32 [[D]], [[TMP0]]
+; CHECK-NEXT:    ret i32 [[SUB6]]
+;
 entry:
   %b.neg = sub i32 0, %b		; <i32> [#uses=1]
   %c.neg = sub i32 0, %c		; <i32> [#uses=1]