[llvm] Rematerialize load RISCV backend (PR #73910)

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git-clang-format --diff 511ba45a47d6f9e48ad364181830c9fb974135b2 13a9981660d9a1149461a5b4851cadeeeafa728a -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 169283e139..fc15b9653d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -47,10 +47,11 @@ static cl::opt<bool> PreferWholeRegisterMove(
     "riscv-prefer-whole-register-move", cl::init(false), cl::Hidden,
     cl::desc("Prefer whole register move for vector registers."));
 
-static cl::opt<bool> AggressiveLoadRemat(
-    "riscv-enable-load-remat-aggressive", cl::init(true), cl::Hidden,
-    cl::desc("Rematerialize load aggressively"));
-    
+static cl::opt<bool>
+    AggressiveLoadRemat("riscv-enable-load-remat-aggressive", cl::init(true),
+                        cl::Hidden,
+                        cl::desc("Rematerialize load aggressively"));
+
 static cl::opt<MachineTraceStrategy> ForceMachineCombinerStrategy(
     "riscv-force-machine-combiner-strategy", cl::Hidden,
     cl::desc("Force machine combiner to use a specific strategy for machine "
@@ -1587,7 +1588,7 @@ bool RISCVInstrInfo::isReallyTriviallyReMaterializable(
   MachineInstr *UseMI = &*MRI.use_instr_begin(Dest.getReg());
   MachineBasicBlock::const_iterator DefItr(MI);
   MachineBasicBlock::const_iterator UseItr(UseMI);
-  
+
   const MachineBasicBlock *MBB = nullptr;
   if ((MBB = MI.getParent()) != UseMI->getParent())
     return false;
@@ -1611,7 +1612,7 @@ bool RISCVInstrInfo::isReallyTriviallyReMaterializable(
     return true;
   }
 
-return false;
+  return false;
 }
 
 std::optional<DestSourcePair>

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https://github.com/llvm/llvm-project/pull/73910