[llvm] [X86][MC]Support Enc/Dec for EGPR for Promoted BMI instructions (PR #73899)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 22:08:33 PST 2023
https://github.com/XinWang10 created https://github.com/llvm/llvm-project/pull/73899
R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958,
This patch
supports the encoding for promoted BMI instructions in EVEX space,
RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
>From fccdefcb9cd824097d1920b264406588f0a21e1b Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 29 Nov 2023 20:12:36 -0800
Subject: [PATCH] [X86][MC]Support Enc/Dec for EGPR for Promoted BMI
instructions
---
.../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 6 +-
llvm/lib/Target/X86/X86InstrArithmetic.td | 58 +++++--
llvm/lib/Target/X86/X86InstrInfo.td | 3 +
llvm/lib/Target/X86/X86InstrMisc.td | 152 ++++++++++--------
llvm/lib/Target/X86/X86InstrShiftRotate.td | 59 ++++---
llvm/test/MC/Disassembler/X86/apx/andn.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/bextr.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/blsi.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/blsmsk.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/blsr.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/bzhi.txt | 18 +++
.../MC/Disassembler/X86/apx/evex-format.txt | 12 ++
llvm/test/MC/Disassembler/X86/apx/mulx.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/pdep.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/pext.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/rorx.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/sarx.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/shlx.txt | 18 +++
llvm/test/MC/Disassembler/X86/apx/shrx.txt | 18 +++
llvm/test/MC/X86/apx/andn-att.s | 20 +++
llvm/test/MC/X86/apx/andn-intel.s | 17 ++
llvm/test/MC/X86/apx/bextr-att.s | 20 +++
llvm/test/MC/X86/apx/bextr-intel.s | 17 ++
llvm/test/MC/X86/apx/blsi-att.s | 20 +++
llvm/test/MC/X86/apx/blsi-intel.s | 17 ++
llvm/test/MC/X86/apx/blsmsk-att.s | 20 +++
llvm/test/MC/X86/apx/blsmsk-intel.s | 17 ++
llvm/test/MC/X86/apx/blsr-att.s | 20 +++
llvm/test/MC/X86/apx/blsr-intel.s | 17 ++
llvm/test/MC/X86/apx/bzhi-att.s | 20 +++
llvm/test/MC/X86/apx/bzhi-intel.s | 17 ++
llvm/test/MC/X86/apx/evex-format-att.s | 12 ++
llvm/test/MC/X86/apx/evex-format-intel.s | 12 ++
llvm/test/MC/X86/apx/mulx-att.s | 20 +++
llvm/test/MC/X86/apx/mulx-intel.s | 17 ++
llvm/test/MC/X86/apx/pdep-att.s | 20 +++
llvm/test/MC/X86/apx/pdep-intel.s | 17 ++
llvm/test/MC/X86/apx/pext-att.s | 20 +++
llvm/test/MC/X86/apx/pext-intel.s | 17 ++
llvm/test/MC/X86/apx/rorx-att.s | 20 +++
llvm/test/MC/X86/apx/rorx-intel.s | 17 ++
llvm/test/MC/X86/apx/sarx-att.s | 20 +++
llvm/test/MC/X86/apx/sarx-intel.s | 17 ++
llvm/test/MC/X86/apx/shlx-att.s | 20 +++
llvm/test/MC/X86/apx/shlx-intel.s | 17 ++
llvm/test/MC/X86/apx/shrx-att.s | 20 +++
llvm/test/MC/X86/apx/shrx-intel.s | 17 ++
llvm/test/TableGen/x86-fold-tables.inc | 26 +++
48 files changed, 945 insertions(+), 110 deletions(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/andn.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/bextr.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/blsi.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/blsmsk.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/blsr.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/bzhi.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/mulx.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/pdep.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/pext.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/rorx.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/sarx.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/shlx.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/shrx.txt
create mode 100644 llvm/test/MC/X86/apx/andn-att.s
create mode 100644 llvm/test/MC/X86/apx/andn-intel.s
create mode 100644 llvm/test/MC/X86/apx/bextr-att.s
create mode 100644 llvm/test/MC/X86/apx/bextr-intel.s
create mode 100644 llvm/test/MC/X86/apx/blsi-att.s
create mode 100644 llvm/test/MC/X86/apx/blsi-intel.s
create mode 100644 llvm/test/MC/X86/apx/blsmsk-att.s
create mode 100644 llvm/test/MC/X86/apx/blsmsk-intel.s
create mode 100644 llvm/test/MC/X86/apx/blsr-att.s
create mode 100644 llvm/test/MC/X86/apx/blsr-intel.s
create mode 100644 llvm/test/MC/X86/apx/bzhi-att.s
create mode 100644 llvm/test/MC/X86/apx/bzhi-intel.s
create mode 100644 llvm/test/MC/X86/apx/mulx-att.s
create mode 100644 llvm/test/MC/X86/apx/mulx-intel.s
create mode 100644 llvm/test/MC/X86/apx/pdep-att.s
create mode 100644 llvm/test/MC/X86/apx/pdep-intel.s
create mode 100644 llvm/test/MC/X86/apx/pext-att.s
create mode 100644 llvm/test/MC/X86/apx/pext-intel.s
create mode 100644 llvm/test/MC/X86/apx/rorx-att.s
create mode 100644 llvm/test/MC/X86/apx/rorx-intel.s
create mode 100644 llvm/test/MC/X86/apx/sarx-att.s
create mode 100644 llvm/test/MC/X86/apx/sarx-intel.s
create mode 100644 llvm/test/MC/X86/apx/shlx-att.s
create mode 100644 llvm/test/MC/X86/apx/shlx-intel.s
create mode 100644 llvm/test/MC/X86/apx/shrx-att.s
create mode 100644 llvm/test/MC/X86/apx/shrx-intel.s
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 1f130c22298ed47..b6ebbcf56aef73d 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1115,10 +1115,10 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
case X86II::MRMSrcMem4VOp3: {
// Instruction format for 4VOp3:
// src1(ModR/M), MemAddr, src3(VEX_4V)
- Prefix.setR(MI, CurOp++);
+ Prefix.setRR2(MI, CurOp++);
Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
- Prefix.set4V(MI, CurOp + X86::AddrNumOperands);
+ Prefix.set4VV2(MI, CurOp + X86::AddrNumOperands);
break;
}
case X86II::MRMSrcMemOp4: {
@@ -1189,7 +1189,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
// src1(ModR/M), src2(ModR/M), src3(VEX_4V)
Prefix.setRR2(MI, CurOp++);
Prefix.setBB2(MI, CurOp++);
- Prefix.set4V(MI, CurOp++);
+ Prefix.set4VV2(MI, CurOp++);
break;
}
case X86II::MRMSrcRegOp4: {
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 48188da291ded0a..56cbc13eaaec8d6 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -1289,21 +1289,34 @@ def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2),
//
multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
PatFrag ld_frag, X86FoldableSchedWrite sched> {
+let Predicates = [HasBMI, NoEGPR] in {
def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
- Sched<[sched]>;
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
+ VEX_4V, Sched<[sched]>;
def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, EFLAGS,
- (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
- Sched<[sched.Folded, sched.ReadAfterFold]>;
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, EFLAGS,
+ (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
+ VEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
+}
+let Predicates = [HasBMI, HasEGPR, In64BitMode] in {
+ def rr_EVEX : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
+ EVEX_4V, Sched<[sched]>;
+ def rm_EVEX : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, EFLAGS,
+ (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
+ EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
+}
}
// Complexity is reduced to give and with immediate a chance to match first.
-let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in {
- defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V;
- defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, REX_W;
+let Defs = [EFLAGS], AddedComplexity = -6 in {
+ defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS;
+ defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, REX_W;
}
let Predicates = [HasBMI], AddedComplexity = -6 in {
@@ -1323,6 +1336,7 @@ let Predicates = [HasBMI], AddedComplexity = -6 in {
multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
X86FoldableSchedWrite sched> {
let hasSideEffects = 0 in {
+let Predicates = [HasBMI2, NoEGPR] in {
def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
[]>, T8XD, VEX_4V, Sched<[WriteIMulH, sched]>;
@@ -1346,15 +1360,27 @@ let hasSideEffects = 0 in {
def Hrm : PseudoI<(outs RC:$dst), (ins x86memop:$src),
[]>, Sched<[sched.Folded]>;
}
+let Predicates = [HasBMI2, HasEGPR, In64BitMode] in
+ def rr#_EVEX : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
+ !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
+ []>, T8XD, EVEX_4V, Sched<[WriteIMulH, sched]>;
+let Predicates = [HasBMI2, HasEGPR, In64BitMode], mayLoad = 1 in
+ def rm#_EVEX : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
+ !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
+ []>, T8XD, EVEX_4V,
+ Sched<[WriteIMulHLd, sched.Folded,
+ // Memory operand.
+ ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+ // Implicit read of EDX/RDX
+ sched.ReadAfterFold]>;
}
-
-let Predicates = [HasBMI2] in {
- let Uses = [EDX] in
- defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>;
- let Uses = [RDX] in
- defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, REX_W;
}
+let Uses = [EDX] in
+ defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>;
+let Uses = [RDX] in
+ defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, REX_W;
+
//===----------------------------------------------------------------------===//
// ADCX and ADOX Instructions
//
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 9046b6af463acf9..988e2a6707c0009 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -878,6 +878,9 @@ def relocImm : ComplexPattern<iAny, 1, "selectRelocImm",
// X86 Instruction Predicate Definitions.
def TruePredicate : Predicate<"true">;
+def HasEGPR : Predicate<"Subtarget->hasEGPR()">;
+def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
+
def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 32aa82fc93ca302..764d4bd6da2a1df 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1214,19 +1214,19 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
RegisterClass RC, X86MemOperand x86memop,
- X86FoldableSchedWrite sched> {
+ X86FoldableSchedWrite sched, string Suffix = ""> {
let hasSideEffects = 0 in {
- def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
- !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
- T8PS, VEX_4V, Sched<[sched]>;
+ def rr#Suffix : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
+ !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
+ T8PS, VEX_4V, Sched<[sched]>;
let mayLoad = 1 in
- def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
- !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
- T8PS, VEX_4V, Sched<[sched.Folded]>;
+ def rm#Suffix : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
+ !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
+ T8PS, VEX_4V, Sched<[sched.Folded]>;
}
}
-let Predicates = [HasBMI], Defs = [EFLAGS] in {
+let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in {
defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>;
defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, REX_W;
defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>;
@@ -1235,6 +1235,15 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, REX_W;
}
+let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in {
+ defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX;
+ defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX;
+ defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX;
+ defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX;
+ defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX;
+ defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX;
+}
+
//===----------------------------------------------------------------------===//
// Pattern fragments to auto generate BMI instructions.
//===----------------------------------------------------------------------===//
@@ -1292,56 +1301,50 @@ let Predicates = [HasBMI] in {
(BLSI64rr GR64:$src)>;
}
-multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC,
- X86MemOperand x86memop, SDNode OpNode,
- PatFrag ld_frag, X86FoldableSchedWrite Sched> {
- def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
- T8PS, VEX, Sched<[Sched]>;
- def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)),
- (implicit EFLAGS)]>, T8PS, VEX,
- Sched<[Sched.Folded,
- // x86memop:$src1
- ReadDefault, ReadDefault, ReadDefault, ReadDefault,
- ReadDefault,
- // RC:$src2
- Sched.ReadAfterFold]>;
+multiclass bmi4VOp3_base<bits<8> opc, string mnemonic, RegisterClass RC,
+ X86MemOperand x86memop, SDPatternOperator OpNode,
+ PatFrag ld_frag, X86FoldableSchedWrite Sched,
+ string Suffix = ""> {
+ def rr#Suffix : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
+ T8PS, VEX, Sched<[Sched]>;
+let mayLoad = 1 in
+ def rm#Suffix : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)),
+ (implicit EFLAGS)]>, T8PS, VEX,
+ Sched<[Sched.Folded,
+ // x86memop:$src1
+ ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+ ReadDefault,
+ // RC:$src2
+ Sched.ReadAfterFold]>;
}
-let Predicates = [HasBMI], Defs = [EFLAGS] in {
- defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem,
- X86bextr, loadi32, WriteBEXTR>;
- defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem,
- X86bextr, loadi64, WriteBEXTR>, REX_W;
-}
-
-multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
- X86MemOperand x86memop, SDNode Int,
- PatFrag ld_frag, X86FoldableSchedWrite Sched> {
- def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
- T8PS, VEX, Sched<[Sched]>;
- def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
- (implicit EFLAGS)]>, T8PS, VEX,
- Sched<[Sched.Folded,
- // x86memop:$src1
- ReadDefault, ReadDefault, ReadDefault, ReadDefault,
- ReadDefault,
- // RC:$src2
- Sched.ReadAfterFold]>;
-}
-
-let Predicates = [HasBMI2], Defs = [EFLAGS] in {
- defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
- X86bzhi, loadi32, WriteBZHI>;
- defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
- X86bzhi, loadi64, WriteBZHI>, REX_W;
+let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in {
+ defm BEXTR32 : bmi4VOp3_base<0xF7, "bextr{l}", GR32, i32mem,
+ X86bextr, loadi32, WriteBEXTR>;
+ defm BEXTR64 : bmi4VOp3_base<0xF7, "bextr{q}", GR64, i64mem,
+ X86bextr, loadi64, WriteBEXTR>, REX_W;
+}
+let Predicates = [HasBMI2, NoEGPR], Defs = [EFLAGS] in {
+ defm BZHI32 : bmi4VOp3_base<0xF5, "bzhi{l}", GR32, i32mem,
+ X86bzhi, loadi32, WriteBZHI>;
+ defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem,
+ X86bzhi, loadi64, WriteBZHI>, REX_W;
+}
+let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in {
+ defm BEXTR32 : bmi4VOp3_base<0xF7, "bextr{l}", GR32, i32mem,
+ X86bextr, loadi32, WriteBEXTR, "_EVEX">, EVEX;
+ defm BEXTR64 : bmi4VOp3_base<0xF7, "bextr{q}", GR64, i64mem,
+ X86bextr, loadi64, WriteBEXTR, "_EVEX">, EVEX, REX_W;
+}
+let Predicates = [HasBMI2, HasEGPR], Defs = [EFLAGS] in {
+ defm BZHI32 : bmi4VOp3_base<0xF5, "bzhi{l}", GR32, i32mem,
+ X86bzhi, loadi32, WriteBZHI, "_EVEX">, EVEX;
+ defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem,
+ X86bzhi, loadi64, WriteBZHI, "_EVEX">, EVEX, REX_W;
}
def CountTrailingOnes : SDNodeXForm<imm, [{
@@ -1383,19 +1386,19 @@ let Predicates = [HasBMI2, NoTBM] in {
}
multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
- X86MemOperand x86memop, SDNode OpNode,
- PatFrag ld_frag> {
- def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
- VEX_4V, Sched<[WriteALU]>;
- def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
- !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
- VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
-}
-
-let Predicates = [HasBMI2] in {
+ X86MemOperand x86memop, SDPatternOperator OpNode,
+ PatFrag ld_frag, string Suffix = ""> {
+ def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
+ VEX_4V, Sched<[WriteALU]>;
+ def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
+ !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
+ VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
+}
+
+let Predicates = [HasBMI2, NoEGPR] in {
defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
X86pdep, loadi32>, T8XD;
defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
@@ -1406,6 +1409,17 @@ let Predicates = [HasBMI2] in {
X86pext, loadi64>, T8XS, REX_W;
}
+let Predicates = [HasBMI2, HasEGPR] in {
+ defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
+ X86pdep, loadi32, "_EVEX">, T8XD, EVEX;
+ defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
+ X86pdep, loadi64, "_EVEX">, T8XD, REX_W, EVEX;
+ defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
+ X86pext, loadi32, "_EVEX">, T8XS, EVEX;
+ defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
+ X86pext, loadi64, "_EVEX">, T8XS, REX_W, EVEX;
+}
+
//===----------------------------------------------------------------------===//
// Lightweight Profiling Instructions
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index e416e4495e22778..48bf23f8cbf7b2f 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -824,38 +824,40 @@ def ROT64L2R_imm8 : SDNodeXForm<imm, [{
// NOTE: We use WriteShift for these rotates as they avoid the stalls
// of many of the older x86 rotate instructions.
-multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
+multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop,
+ string Suffix = ""> {
let hasSideEffects = 0 in {
- def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
- !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>, TAXD, VEX, Sched<[WriteShift]>;
+ def ri#Suffix : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
+ TAXD, VEX, Sched<[WriteShift]>;
let mayLoad = 1 in
- def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
- (ins x86memop:$src1, u8imm:$src2),
- !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>, TAXD, VEX, Sched<[WriteShiftLd]>;
+ def mi#Suffix : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
+ (ins x86memop:$src1, u8imm:$src2),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
+ TAXD, VEX, Sched<[WriteShiftLd]>;
}
}
-multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
+multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop,
+ string Suffix = ""> {
let hasSideEffects = 0 in {
- def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
- !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
- VEX, Sched<[WriteShift]>;
+ def rr#Suffix : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
+ VEX, Sched<[WriteShift]>;
let mayLoad = 1 in
- def rm : I<0xF7, MRMSrcMem4VOp3,
- (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
- !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
- VEX, Sched<[WriteShift.Folded,
- // x86memop:$src1
- ReadDefault, ReadDefault, ReadDefault, ReadDefault,
- ReadDefault,
- // RC:$src2
- WriteShift.ReadAfterFold]>;
+ def rm#Suffix : I<0xF7, MRMSrcMem4VOp3,
+ (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
+ VEX, Sched<[WriteShift.Folded,
+ // x86memop:$src1
+ ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+ ReadDefault,
+ // RC:$src2
+ WriteShift.ReadAfterFold]>;
}
}
-let Predicates = [HasBMI2] in {
+let Predicates = [HasBMI2, NoEGPR] in {
defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, REX_W;
defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
@@ -864,7 +866,20 @@ let Predicates = [HasBMI2] in {
defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, REX_W;
defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, REX_W;
+}
+let Predicates = [HasBMI2, HasEGPR] in {
+ defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem, "_EVEX">, EVEX;
+ defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem, "_EVEX">, REX_W, EVEX;
+ defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem, "_EVEX">, T8XS, EVEX;
+ defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem, "_EVEX">, T8XS, REX_W, EVEX;
+ defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem, "_EVEX">, T8XD, EVEX;
+ defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem, "_EVEX">, T8XD, REX_W, EVEX;
+ defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem, "_EVEX">, T8PD, EVEX;
+ defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8PD, REX_W, EVEX;
+}
+
+let Predicates = [HasBMI2] in {
// Prefer RORX which is non-destructive and doesn't update EFLAGS.
let AddedComplexity = 10 in {
def : Pat<(rotr GR32:$src, (i8 imm:$shamt)),
diff --git a/llvm/test/MC/Disassembler/X86/apx/andn.txt b/llvm/test/MC/Disassembler/X86/apx/andn.txt
new file mode 100644
index 000000000000000..8b943d2a0ac44c9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/andn.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: andnl %r18d, %r22d, %r26d
+# INTEL: andn r26d, r22d, r18d
+0x62,0x6a,0x4c,0x00,0xf2,0xd2
+
+# ATT: andnq %r19, %r23, %r27
+# INTEL: andn r27, r23, r19
+0x62,0x6a,0xc4,0x00,0xf2,0xdb
+
+# ATT: andnl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: andn r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x68,0x00,0xf2,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: andnq 291(%r28,%r29,4), %r19, %r23
+# INTEL: andn r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe0,0x00,0xf2,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/bextr.txt b/llvm/test/MC/Disassembler/X86/apx/bextr.txt
new file mode 100644
index 000000000000000..abd92864b315e36
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/bextr.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: bextrl %r18d, %r22d, %r26d
+# INTEL: bextr r26d, r22d, r18d
+0x62,0x6a,0x6c,0x00,0xf7,0xd6
+
+# ATT: bextrl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: bextr r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x68,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: bextrq %r19, %r23, %r27
+# INTEL: bextr r27, r23, r19
+0x62,0x6a,0xe4,0x00,0xf7,0xdf
+
+# ATT: bextrq %r19, 291(%r28,%r29,4), %r23
+# INTEL: bextr r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe0,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/blsi.txt b/llvm/test/MC/Disassembler/X86/apx/blsi.txt
new file mode 100644
index 000000000000000..254ec90caea5152
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/blsi.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: blsil %r18d, %r22d
+# INTEL: blsi r22d, r18d
+0x62,0xfa,0x4c,0x00,0xf3,0xda
+
+# ATT: blsiq %r19, %r23
+# INTEL: blsi r23, r19
+0x62,0xfa,0xc4,0x00,0xf3,0xdb
+
+# ATT: blsil 291(%r28,%r29,4), %r18d
+# INTEL: blsi r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x9a,0x68,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: blsiq 291(%r28,%r29,4), %r19
+# INTEL: blsi r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x9a,0xe0,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt b/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt
new file mode 100644
index 000000000000000..5e47d3d3d625eb5
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/blsmsk.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: blsmskl %r18d, %r22d
+# INTEL: blsmsk r22d, r18d
+0x62,0xfa,0x4c,0x00,0xf3,0xd2
+
+# ATT: blsmskq %r19, %r23
+# INTEL: blsmsk r23, r19
+0x62,0xfa,0xc4,0x00,0xf3,0xd3
+
+# ATT: blsmskl 291(%r28,%r29,4), %r18d
+# INTEL: blsmsk r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x9a,0x68,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: blsmskq 291(%r28,%r29,4), %r19
+# INTEL: blsmsk r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x9a,0xe0,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/blsr.txt b/llvm/test/MC/Disassembler/X86/apx/blsr.txt
new file mode 100644
index 000000000000000..37df4306da26edb
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/blsr.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: blsrl %r18d, %r22d
+# INTEL: blsr r22d, r18d
+0x62,0xfa,0x4c,0x00,0xf3,0xca
+
+# ATT: blsrq %r19, %r23
+# INTEL: blsr r23, r19
+0x62,0xfa,0xc4,0x00,0xf3,0xcb
+
+# ATT: blsrl 291(%r28,%r29,4), %r18d
+# INTEL: blsr r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x9a,0x68,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: blsrq 291(%r28,%r29,4), %r19
+# INTEL: blsr r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x9a,0xe0,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt
new file mode 100644
index 000000000000000..44f496e3cc08401
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: bzhil %r18d, %r22d, %r26d
+# INTEL: bzhi r26d, r22d, r18d
+0x62,0x6a,0x6c,0x00,0xf5,0xd6
+
+# ATT: bzhil %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: bzhi r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x68,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: bzhiq %r19, %r23, %r27
+# INTEL: bzhi r27, r23, r19
+0x62,0x6a,0xe4,0x00,0xf5,0xdf
+
+# ATT: bzhiq %r19, 291(%r28,%r29,4), %r23
+# INTEL: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
index ee2c2c5bdf909c1..389b22cb4a223d3 100644
--- a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
@@ -62,8 +62,20 @@
# INTEL: vpslldq zmm0, zmmword ptr [r16 + r17], 0
0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00
+## MRMSrcMem4VOp3
+
+# ATT: bzhiq %r19, 291(%r28,%r29,4), %r23
+# INTEL: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00
+
## MRMDestReg
# ATT: vextractps $1, %xmm16, %r16d
# INTEL: vextractps r16d, xmm16, 1
0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01
+
+## MRMSrcReg4VOp3
+
+# ATT: bzhiq %r19, %r23, %r27
+# INTEL: bzhi r27, r23, r19
+0x62,0x6a,0xe4,0x00,0xf5,0xdf
diff --git a/llvm/test/MC/Disassembler/X86/apx/mulx.txt b/llvm/test/MC/Disassembler/X86/apx/mulx.txt
new file mode 100644
index 000000000000000..5d9b53b99a71b65
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/mulx.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: mulxl %r18d, %r22d, %r26d
+# INTEL: mulx r26d, r22d, r18d
+0x62,0x6a,0x4f,0x00,0xf6,0xd2
+
+# ATT: mulxq %r19, %r23, %r27
+# INTEL: mulx r27, r23, r19
+0x62,0x6a,0xc7,0x00,0xf6,0xdb
+
+# ATT: mulxl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: mulxq 291(%r28,%r29,4), %r19, %r23
+# INTEL: mulx r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/pdep.txt b/llvm/test/MC/Disassembler/X86/apx/pdep.txt
new file mode 100644
index 000000000000000..87268fe5e27dd8c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/pdep.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: pdepl %r18d, %r22d, %r26d
+# INTEL: pdep r26d, r22d, r18d
+0x62,0x6a,0x4f,0x00,0xf5,0xd2
+
+# ATT: pdepq %r19, %r23, %r27
+# INTEL: pdep r27, r23, r19
+0x62,0x6a,0xc7,0x00,0xf5,0xdb
+
+# ATT: pdepl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: pdepq 291(%r28,%r29,4), %r19, %r23
+# INTEL: pdep r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/pext.txt b/llvm/test/MC/Disassembler/X86/apx/pext.txt
new file mode 100644
index 000000000000000..6c5860aa8128122
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/pext.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: pextl %r18d, %r22d, %r26d
+# INTEL: pext r26d, r22d, r18d
+0x62,0x6a,0x4e,0x00,0xf5,0xd2
+
+# ATT: pextq %r19, %r23, %r27
+# INTEL: pext r27, r23, r19
+0x62,0x6a,0xc6,0x00,0xf5,0xdb
+
+# ATT: pextl 291(%r28,%r29,4), %r18d, %r22d
+# INTEL: pext r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: pextq 291(%r28,%r29,4), %r19, %r23
+# INTEL: pext r23, r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/rorx.txt b/llvm/test/MC/Disassembler/X86/apx/rorx.txt
new file mode 100644
index 000000000000000..9860deaea86bdda
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/rorx.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: rorxl $123, %r18d, %r22d
+# INTEL: rorx r22d, r18d, 123
+0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b
+
+# ATT: rorxq $123, %r19, %r23
+# INTEL: rorx r23, r19, 123
+0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b
+
+# ATT: rorxl $123, 291(%r28,%r29,4), %r18d
+# INTEL: rorx r18d, dword ptr [r28 + 4*r29 + 291], 123
+0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: rorxq $123, 291(%r28,%r29,4), %r19
+# INTEL: rorx r19, qword ptr [r28 + 4*r29 + 291], 123
+0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b
diff --git a/llvm/test/MC/Disassembler/X86/apx/sarx.txt b/llvm/test/MC/Disassembler/X86/apx/sarx.txt
new file mode 100644
index 000000000000000..20018f4d4b12839
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sarx.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: sarxl %r18d, %r22d, %r26d
+# INTEL: sarx r26d, r22d, r18d
+0x62,0x6a,0x6e,0x00,0xf7,0xd6
+
+# ATT: sarxl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: sarxq %r19, %r23, %r27
+# INTEL: sarx r27, r23, r19
+0x62,0x6a,0xe6,0x00,0xf7,0xdf
+
+# ATT: sarxq %r19, 291(%r28,%r29,4), %r23
+# INTEL: sarx r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/shlx.txt b/llvm/test/MC/Disassembler/X86/apx/shlx.txt
new file mode 100644
index 000000000000000..f6d6250bd06318f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/shlx.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: shlxl %r18d, %r22d, %r26d
+# INTEL: shlx r26d, r22d, r18d
+0x62,0x6a,0x6d,0x00,0xf7,0xd6
+
+# ATT: shlxl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: shlxq %r19, %r23, %r27
+# INTEL: shlx r27, r23, r19
+0x62,0x6a,0xe5,0x00,0xf7,0xdf
+
+# ATT: shlxq %r19, 291(%r28,%r29,4), %r23
+# INTEL: shlx r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/shrx.txt b/llvm/test/MC/Disassembler/X86/apx/shrx.txt
new file mode 100644
index 000000000000000..09750e05c127e6f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/shrx.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: shrxl %r18d, %r22d, %r26d
+# INTEL: shrx r26d, r22d, r18d
+0x62,0x6a,0x6f,0x00,0xf7,0xd6
+
+# ATT: shrxl %r18d, 291(%r28,%r29,4), %r22d
+# INTEL: shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: shrxq %r19, %r23, %r27
+# INTEL: shrx r27, r23, r19
+0x62,0x6a,0xe7,0x00,0xf7,0xdf
+
+# ATT: shrxq %r19, 291(%r28,%r29,4), %r23
+# INTEL: shrx r23, qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/andn-att.s b/llvm/test/MC/X86/apx/andn-att.s
new file mode 100644
index 000000000000000..d68cee8bcf1f72c
--- /dev/null
+++ b/llvm/test/MC/X86/apx/andn-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: andnl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2]
+ andnl %r18d, %r22d, %r26d
+
+# CHECK: andnq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xc4,0x00,0xf2,0xdb]
+ andnq %r19, %r23, %r27
+
+# CHECK: andnl 291(%r28,%r29,4), %r18d, %r22d
+# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf2,0xb4,0xac,0x23,0x01,0x00,0x00]
+ andnl 291(%r28,%r29,4), %r18d, %r22d
+
+# CHECK: andnq 291(%r28,%r29,4), %r19, %r23
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf2,0xbc,0xac,0x23,0x01,0x00,0x00]
+ andnq 291(%r28,%r29,4), %r19, %r23
diff --git a/llvm/test/MC/X86/apx/andn-intel.s b/llvm/test/MC/X86/apx/andn-intel.s
new file mode 100644
index 000000000000000..583e6e763b1eca5
--- /dev/null
+++ b/llvm/test/MC/X86/apx/andn-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: andn r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2]
+ andn r26d, r22d, r18d
+
+# CHECK: andn r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xc4,0x00,0xf2,0xdb]
+ andn r27, r23, r19
+
+# CHECK: andn r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf2,0xb4,0xac,0x23,0x01,0x00,0x00]
+ andn r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: andn r23, r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf2,0xbc,0xac,0x23,0x01,0x00,0x00]
+ andn r23, r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/bextr-att.s b/llvm/test/MC/X86/apx/bextr-att.s
new file mode 100644
index 000000000000000..6095ffa389a34cf
--- /dev/null
+++ b/llvm/test/MC/X86/apx/bextr-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: bextrl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6]
+ bextrl %r18d, %r22d, %r26d
+
+# CHECK: bextrl %r18d, 291(%r28,%r29,4), %r22d
+# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ bextrl %r18d, 291(%r28,%r29,4), %r22d
+
+# CHECK: bextrq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf7,0xdf]
+ bextrq %r19, %r23, %r27
+
+# CHECK: bextrq %r19, 291(%r28,%r29,4), %r23
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ bextrq %r19, 291(%r28,%r29,4), %r23
diff --git a/llvm/test/MC/X86/apx/bextr-intel.s b/llvm/test/MC/X86/apx/bextr-intel.s
new file mode 100644
index 000000000000000..af70c00c1d631d3
--- /dev/null
+++ b/llvm/test/MC/X86/apx/bextr-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: bextr r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6]
+ bextr r26d, r22d, r18d
+
+# CHECK: bextr r22d, dword ptr [r28 + 4*r29 + 291], r18d
+# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ bextr r22d, dword ptr [r28 + 4*r29 + 291], r18d
+
+# CHECK: bextr r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf7,0xdf]
+ bextr r27, r23, r19
+
+# CHECK: bextr r23, qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ bextr r23, qword ptr [r28 + 4*r29 + 291], r19
diff --git a/llvm/test/MC/X86/apx/blsi-att.s b/llvm/test/MC/X86/apx/blsi-att.s
new file mode 100644
index 000000000000000..65b2fd2b4d09b66
--- /dev/null
+++ b/llvm/test/MC/X86/apx/blsi-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: blsil %r18d, %r22d
+# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xda]
+ blsil %r18d, %r22d
+
+# CHECK: blsiq %r19, %r23
+# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xdb]
+ blsiq %r19, %r23
+
+# CHECK: blsil 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00]
+ blsil 291(%r28,%r29,4), %r18d
+
+# CHECK: blsiq 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00]
+ blsiq 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/blsi-intel.s b/llvm/test/MC/X86/apx/blsi-intel.s
new file mode 100644
index 000000000000000..edf5711cc74b573
--- /dev/null
+++ b/llvm/test/MC/X86/apx/blsi-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: blsi r22d, r18d
+# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xda]
+ blsi r22d, r18d
+
+# CHECK: blsi r23, r19
+# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xdb]
+ blsi r23, r19
+
+# CHECK: blsi r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00]
+ blsi r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: blsi r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x9c,0xac,0x23,0x01,0x00,0x00]
+ blsi r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/blsmsk-att.s b/llvm/test/MC/X86/apx/blsmsk-att.s
new file mode 100644
index 000000000000000..710fcabddcc3abc
--- /dev/null
+++ b/llvm/test/MC/X86/apx/blsmsk-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: blsmskl %r18d, %r22d
+# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xd2]
+ blsmskl %r18d, %r22d
+
+# CHECK: blsmskq %r19, %r23
+# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xd3]
+ blsmskq %r19, %r23
+
+# CHECK: blsmskl 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00]
+ blsmskl 291(%r28,%r29,4), %r18d
+
+# CHECK: blsmskq 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00]
+ blsmskq 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/blsmsk-intel.s b/llvm/test/MC/X86/apx/blsmsk-intel.s
new file mode 100644
index 000000000000000..bb8197d3d41026d
--- /dev/null
+++ b/llvm/test/MC/X86/apx/blsmsk-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: blsmsk r22d, r18d
+# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xd2]
+ blsmsk r22d, r18d
+
+# CHECK: blsmsk r23, r19
+# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xd3]
+ blsmsk r23, r19
+
+# CHECK: blsmsk r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00]
+ blsmsk r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: blsmsk r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x94,0xac,0x23,0x01,0x00,0x00]
+ blsmsk r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/blsr-att.s b/llvm/test/MC/X86/apx/blsr-att.s
new file mode 100644
index 000000000000000..c9ca56149cf1a8e
--- /dev/null
+++ b/llvm/test/MC/X86/apx/blsr-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: blsrl %r18d, %r22d
+# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xca]
+ blsrl %r18d, %r22d
+
+# CHECK: blsrq %r19, %r23
+# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xcb]
+ blsrq %r19, %r23
+
+# CHECK: blsrl 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00]
+ blsrl 291(%r28,%r29,4), %r18d
+
+# CHECK: blsrq 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00]
+ blsrq 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/blsr-intel.s b/llvm/test/MC/X86/apx/blsr-intel.s
new file mode 100644
index 000000000000000..acbfb81964614eb
--- /dev/null
+++ b/llvm/test/MC/X86/apx/blsr-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: blsr r22d, r18d
+# CHECK: encoding: [0x62,0xfa,0x4c,0x00,0xf3,0xca]
+ blsr r22d, r18d
+
+# CHECK: blsr r23, r19
+# CHECK: encoding: [0x62,0xfa,0xc4,0x00,0xf3,0xcb]
+ blsr r23, r19
+
+# CHECK: blsr r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x68,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00]
+ blsr r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: blsr r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0xe0,0x00,0xf3,0x8c,0xac,0x23,0x01,0x00,0x00]
+ blsr r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/bzhi-att.s b/llvm/test/MC/X86/apx/bzhi-att.s
new file mode 100644
index 000000000000000..635cfa14e6b4f59
--- /dev/null
+++ b/llvm/test/MC/X86/apx/bzhi-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: bzhil %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf5,0xd6]
+ bzhil %r18d, %r22d, %r26d
+
+# CHECK: bzhil %r18d, 291(%r28,%r29,4), %r22d
+# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00]
+ bzhil %r18d, 291(%r28,%r29,4), %r22d
+
+# CHECK: bzhiq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf]
+ bzhiq %r19, %r23, %r27
+
+# CHECK: bzhiq %r19, 291(%r28,%r29,4), %r23
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ bzhiq %r19, 291(%r28,%r29,4), %r23
diff --git a/llvm/test/MC/X86/apx/bzhi-intel.s b/llvm/test/MC/X86/apx/bzhi-intel.s
new file mode 100644
index 000000000000000..f7ab72dd717ee76
--- /dev/null
+++ b/llvm/test/MC/X86/apx/bzhi-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: bzhi r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf5,0xd6]
+ bzhi r26d, r22d, r18d
+
+# CHECK: bzhi r22d, dword ptr [r28 + 4*r29 + 291], r18d
+# CHECK: encoding: [0x62,0x8a,0x68,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00]
+ bzhi r22d, dword ptr [r28 + 4*r29 + 291], r18d
+
+# CHECK: bzhi r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf]
+ bzhi r27, r23, r19
+
+# CHECK: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ bzhi r23, qword ptr [r28 + 4*r29 + 291], r19
diff --git a/llvm/test/MC/X86/apx/evex-format-att.s b/llvm/test/MC/X86/apx/evex-format-att.s
index aedd09e7e698df2..0b2e860d6ba090a 100644
--- a/llvm/test/MC/X86/apx/evex-format-att.s
+++ b/llvm/test/MC/X86/apx/evex-format-att.s
@@ -60,8 +60,20 @@
# CHECK: encoding: [0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00]
vpslldq $0, (%r16,%r17), %zmm0
+## MRMSrcMem4VOp3
+
+# CHECK: bzhiq %r19, 291(%r28,%r29,4), %r23
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ bzhiq %r19, 291(%r28,%r29,4), %r23
+
## MRMDestReg
# CHECK: vextractps $1, %xmm16, %r16d
# CHECK: encoding: [0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01]
vextractps $1, %xmm16, %r16d
+
+## MRMSrcReg4VOp3
+
+# CHECK: bzhiq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf]
+ bzhiq %r19, %r23, %r27
diff --git a/llvm/test/MC/X86/apx/evex-format-intel.s b/llvm/test/MC/X86/apx/evex-format-intel.s
index aa11a879f4b4c60..ececb7137b1101c 100644
--- a/llvm/test/MC/X86/apx/evex-format-intel.s
+++ b/llvm/test/MC/X86/apx/evex-format-intel.s
@@ -60,8 +60,20 @@
# CHECK: encoding: [0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00]
vpslldq zmm0, zmmword ptr [r16 + r17], 0
+## MRMSrcMem4VOp3
+
+# CHECK: bzhi r23, qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8a,0xe0,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ bzhi r23, qword ptr [r28 + 4*r29 + 291], r19
+
## MRMDestReg
# CHECK: vextractps r16d, xmm16, 1
# CHECK: encoding: [0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01]
vextractps r16d, xmm16, 1
+
+## MRMSrcReg4VOp3
+
+# CHECK: bzhi r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xe4,0x00,0xf5,0xdf]
+ bzhi r27, r23, r19
diff --git a/llvm/test/MC/X86/apx/mulx-att.s b/llvm/test/MC/X86/apx/mulx-att.s
new file mode 100644
index 000000000000000..976a79f469cd6fc
--- /dev/null
+++ b/llvm/test/MC/X86/apx/mulx-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: mulxl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf6,0xd2]
+ mulxl %r18d, %r22d, %r26d
+
+# CHECK: mulxq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf6,0xdb]
+ mulxq %r19, %r23, %r27
+
+# CHECK: mulxl 291(%r28,%r29,4), %r18d, %r22d
+# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00]
+ mulxl 291(%r28,%r29,4), %r18d, %r22d
+
+# CHECK: mulxq 291(%r28,%r29,4), %r19, %r23
+# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00]
+ mulxq 291(%r28,%r29,4), %r19, %r23
diff --git a/llvm/test/MC/X86/apx/mulx-intel.s b/llvm/test/MC/X86/apx/mulx-intel.s
new file mode 100644
index 000000000000000..3db587502915df6
--- /dev/null
+++ b/llvm/test/MC/X86/apx/mulx-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: mulx r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf6,0xd2]
+ mulx r26d, r22d, r18d
+
+# CHECK: mulx r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf6,0xdb]
+ mulx r27, r23, r19
+
+# CHECK: mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf6,0xb4,0xac,0x23,0x01,0x00,0x00]
+ mulx r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: mulx r23, r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf6,0xbc,0xac,0x23,0x01,0x00,0x00]
+ mulx r23, r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/pdep-att.s b/llvm/test/MC/X86/apx/pdep-att.s
new file mode 100644
index 000000000000000..c319b17e47f6fc2
--- /dev/null
+++ b/llvm/test/MC/X86/apx/pdep-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: pdepl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf5,0xd2]
+ pdepl %r18d, %r22d, %r26d
+
+# CHECK: pdepq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf5,0xdb]
+ pdepq %r19, %r23, %r27
+
+# CHECK: pdepl 291(%r28,%r29,4), %r18d, %r22d
+# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00]
+ pdepl 291(%r28,%r29,4), %r18d, %r22d
+
+# CHECK: pdepq 291(%r28,%r29,4), %r19, %r23
+# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ pdepq 291(%r28,%r29,4), %r19, %r23
diff --git a/llvm/test/MC/X86/apx/pdep-intel.s b/llvm/test/MC/X86/apx/pdep-intel.s
new file mode 100644
index 000000000000000..0f9e828c021c3a9
--- /dev/null
+++ b/llvm/test/MC/X86/apx/pdep-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: pdep r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x4f,0x00,0xf5,0xd2]
+ pdep r26d, r22d, r18d
+
+# CHECK: pdep r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xc7,0x00,0xf5,0xdb]
+ pdep r27, r23, r19
+
+# CHECK: pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00]
+ pdep r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: pdep r23, r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ pdep r23, r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/pext-att.s b/llvm/test/MC/X86/apx/pext-att.s
new file mode 100644
index 000000000000000..c07fa1ac2082af2
--- /dev/null
+++ b/llvm/test/MC/X86/apx/pext-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: pextl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x4e,0x00,0xf5,0xd2]
+ pextl %r18d, %r22d, %r26d
+
+# CHECK: pextq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xc6,0x00,0xf5,0xdb]
+ pextq %r19, %r23, %r27
+
+# CHECK: pextl 291(%r28,%r29,4), %r18d, %r22d
+# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00]
+ pextl 291(%r28,%r29,4), %r18d, %r22d
+
+# CHECK: pextq 291(%r28,%r29,4), %r19, %r23
+# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ pextq 291(%r28,%r29,4), %r19, %r23
diff --git a/llvm/test/MC/X86/apx/pext-intel.s b/llvm/test/MC/X86/apx/pext-intel.s
new file mode 100644
index 000000000000000..9a7e7d93094a424
--- /dev/null
+++ b/llvm/test/MC/X86/apx/pext-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: pext r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x4e,0x00,0xf5,0xd2]
+ pext r26d, r22d, r18d
+
+# CHECK: pext r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xc6,0x00,0xf5,0xdb]
+ pext r27, r23, r19
+
+# CHECK: pext r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf5,0xb4,0xac,0x23,0x01,0x00,0x00]
+ pext r22d, r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: pext r23, r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf5,0xbc,0xac,0x23,0x01,0x00,0x00]
+ pext r23, r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/rorx-att.s b/llvm/test/MC/X86/apx/rorx-att.s
new file mode 100644
index 000000000000000..fb613d95c7cb43d
--- /dev/null
+++ b/llvm/test/MC/X86/apx/rorx-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: rorxl $123, %r18d, %r22d
+# CHECK: encoding: [0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b]
+ rorxl $123, %r18d, %r22d
+
+# CHECK: rorxq $123, %r19, %r23
+# CHECK: encoding: [0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b]
+ rorxq $123, %r19, %r23
+
+# CHECK: rorxl $123, 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b]
+ rorxl $123, 291(%r28,%r29,4), %r18d
+
+# CHECK: rorxq $123, 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b]
+ rorxq $123, 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/rorx-intel.s b/llvm/test/MC/X86/apx/rorx-intel.s
new file mode 100644
index 000000000000000..d3e63559cba5793
--- /dev/null
+++ b/llvm/test/MC/X86/apx/rorx-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: rorx r22d, r18d, 123
+# CHECK: encoding: [0x62,0xeb,0x7f,0x08,0xf0,0xf2,0x7b]
+ rorx r22d, r18d, 123
+
+# CHECK: rorx r23, r19, 123
+# CHECK: encoding: [0x62,0xeb,0xff,0x08,0xf0,0xfb,0x7b]
+ rorx r23, r19, 123
+
+# CHECK: rorx r18d, dword ptr [r28 + 4*r29 + 291], 123
+# CHECK: encoding: [0x62,0x8b,0x7b,0x08,0xf0,0x94,0xac,0x23,0x01,0x00,0x00,0x7b]
+ rorx r18d, dword ptr [r28 + 4*r29 + 291], 123
+
+# CHECK: rorx r19, qword ptr [r28 + 4*r29 + 291], 123
+# CHECK: encoding: [0x62,0x8b,0xfb,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00,0x7b]
+ rorx r19, qword ptr [r28 + 4*r29 + 291], 123
diff --git a/llvm/test/MC/X86/apx/sarx-att.s b/llvm/test/MC/X86/apx/sarx-att.s
new file mode 100644
index 000000000000000..a174903d976cbf2
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sarx-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: sarxl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x6e,0x00,0xf7,0xd6]
+ sarxl %r18d, %r22d, %r26d
+
+# CHECK: sarxl %r18d, 291(%r28,%r29,4), %r22d
+# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ sarxl %r18d, 291(%r28,%r29,4), %r22d
+
+# CHECK: sarxq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xe6,0x00,0xf7,0xdf]
+ sarxq %r19, %r23, %r27
+
+# CHECK: sarxq %r19, 291(%r28,%r29,4), %r23
+# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ sarxq %r19, 291(%r28,%r29,4), %r23
diff --git a/llvm/test/MC/X86/apx/sarx-intel.s b/llvm/test/MC/X86/apx/sarx-intel.s
new file mode 100644
index 000000000000000..962b6ec313b9874
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sarx-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sarx r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x6e,0x00,0xf7,0xd6]
+ sarx r26d, r22d, r18d
+
+# CHECK: sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+# CHECK: encoding: [0x62,0x8a,0x6a,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ sarx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+
+# CHECK: sarx r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xe6,0x00,0xf7,0xdf]
+ sarx r27, r23, r19
+
+# CHECK: sarx r23, qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8a,0xe2,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ sarx r23, qword ptr [r28 + 4*r29 + 291], r19
diff --git a/llvm/test/MC/X86/apx/shlx-att.s b/llvm/test/MC/X86/apx/shlx-att.s
new file mode 100644
index 000000000000000..4e28119f083056f
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shlx-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: shlxl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x6d,0x00,0xf7,0xd6]
+ shlxl %r18d, %r22d, %r26d
+
+# CHECK: shlxl %r18d, 291(%r28,%r29,4), %r22d
+# CHECK: encoding: [0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ shlxl %r18d, 291(%r28,%r29,4), %r22d
+
+# CHECK: shlxq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xe5,0x00,0xf7,0xdf]
+ shlxq %r19, %r23, %r27
+
+# CHECK: shlxq %r19, 291(%r28,%r29,4), %r23
+# CHECK: encoding: [0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ shlxq %r19, 291(%r28,%r29,4), %r23
diff --git a/llvm/test/MC/X86/apx/shlx-intel.s b/llvm/test/MC/X86/apx/shlx-intel.s
new file mode 100644
index 000000000000000..9f16918a712dc5e
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shlx-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: shlx r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x6d,0x00,0xf7,0xd6]
+ shlx r26d, r22d, r18d
+
+# CHECK: shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+# CHECK: encoding: [0x62,0x8a,0x69,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ shlx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+
+# CHECK: shlx r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xe5,0x00,0xf7,0xdf]
+ shlx r27, r23, r19
+
+# CHECK: shlx r23, qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8a,0xe1,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ shlx r23, qword ptr [r28 + 4*r29 + 291], r19
diff --git a/llvm/test/MC/X86/apx/shrx-att.s b/llvm/test/MC/X86/apx/shrx-att.s
new file mode 100644
index 000000000000000..d9bb5f84af73d40
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shrx-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: shrxl %r18d, %r22d, %r26d
+# CHECK: encoding: [0x62,0x6a,0x6f,0x00,0xf7,0xd6]
+ shrxl %r18d, %r22d, %r26d
+
+# CHECK: shrxl %r18d, 291(%r28,%r29,4), %r22d
+# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ shrxl %r18d, 291(%r28,%r29,4), %r22d
+
+# CHECK: shrxq %r19, %r23, %r27
+# CHECK: encoding: [0x62,0x6a,0xe7,0x00,0xf7,0xdf]
+ shrxq %r19, %r23, %r27
+
+# CHECK: shrxq %r19, 291(%r28,%r29,4), %r23
+# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ shrxq %r19, 291(%r28,%r29,4), %r23
diff --git a/llvm/test/MC/X86/apx/shrx-intel.s b/llvm/test/MC/X86/apx/shrx-intel.s
new file mode 100644
index 000000000000000..385c530a1108bee
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shrx-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: shrx r26d, r22d, r18d
+# CHECK: encoding: [0x62,0x6a,0x6f,0x00,0xf7,0xd6]
+ shrx r26d, r22d, r18d
+
+# CHECK: shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+# CHECK: encoding: [0x62,0x8a,0x6b,0x00,0xf7,0xb4,0xac,0x23,0x01,0x00,0x00]
+ shrx r22d, dword ptr [r28 + 4*r29 + 291], r18d
+
+# CHECK: shrx r27, r23, r19
+# CHECK: encoding: [0x62,0x6a,0xe7,0x00,0xf7,0xdf]
+ shrx r27, r23, r19
+
+# CHECK: shrx r23, qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8a,0xe3,0x00,0xf7,0xbc,0xac,0x23,0x01,0x00,0x00]
+ shrx r23, qword ptr [r28 + 4*r29 + 291], r19
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index d4515161ee0858a..a764cc064c82868 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -411,7 +411,9 @@ static const X86FoldTableEntry Table1[] = {
{X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16},
{X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16},
{X86::BEXTR32rr, X86::BEXTR32rm, 0},
+ {X86::BEXTR32rr_EVEX, X86::BEXTR32rm_EVEX, 0},
{X86::BEXTR64rr, X86::BEXTR64rm, 0},
+ {X86::BEXTR64rr_EVEX, X86::BEXTR64rm_EVEX, 0},
{X86::BEXTRI32ri, X86::BEXTRI32mi, 0},
{X86::BEXTRI64ri, X86::BEXTRI64mi, 0},
{X86::BLCFILL32rr, X86::BLCFILL32rm, 0},
@@ -427,13 +429,19 @@ static const X86FoldTableEntry Table1[] = {
{X86::BLSFILL32rr, X86::BLSFILL32rm, 0},
{X86::BLSFILL64rr, X86::BLSFILL64rm, 0},
{X86::BLSI32rr, X86::BLSI32rm, 0},
+ {X86::BLSI32rr_EVEX, X86::BLSI32rm_EVEX, 0},
{X86::BLSI64rr, X86::BLSI64rm, 0},
+ {X86::BLSI64rr_EVEX, X86::BLSI64rm_EVEX, 0},
{X86::BLSIC32rr, X86::BLSIC32rm, 0},
{X86::BLSIC64rr, X86::BLSIC64rm, 0},
{X86::BLSMSK32rr, X86::BLSMSK32rm, 0},
+ {X86::BLSMSK32rr_EVEX, X86::BLSMSK32rm_EVEX, 0},
{X86::BLSMSK64rr, X86::BLSMSK64rm, 0},
+ {X86::BLSMSK64rr_EVEX, X86::BLSMSK64rm_EVEX, 0},
{X86::BLSR32rr, X86::BLSR32rm, 0},
+ {X86::BLSR32rr_EVEX, X86::BLSR32rm_EVEX, 0},
{X86::BLSR64rr, X86::BLSR64rm, 0},
+ {X86::BLSR64rr_EVEX, X86::BLSR64rm_EVEX, 0},
{X86::BSF16rr, X86::BSF16rm, 0},
{X86::BSF32rr, X86::BSF32rm, 0},
{X86::BSF64rr, X86::BSF64rm, 0},
@@ -441,7 +449,9 @@ static const X86FoldTableEntry Table1[] = {
{X86::BSR32rr, X86::BSR32rm, 0},
{X86::BSR64rr, X86::BSR64rm, 0},
{X86::BZHI32rr, X86::BZHI32rm, 0},
+ {X86::BZHI32rr_EVEX, X86::BZHI32rm_EVEX, 0},
{X86::BZHI64rr, X86::BZHI64rm, 0},
+ {X86::BZHI64rr_EVEX, X86::BZHI64rm_EVEX, 0},
{X86::CMP16rr, X86::CMP16rm, 0},
{X86::CMP32rr, X86::CMP32rm, 0},
{X86::CMP64rr, X86::CMP64rm, 0},
@@ -578,7 +588,9 @@ static const X86FoldTableEntry Table1[] = {
{X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16},
{X86::RCPSSr, X86::RCPSSm, 0},
{X86::RORX32ri, X86::RORX32mi, 0},
+ {X86::RORX32ri_EVEX, X86::RORX32mi_EVEX, 0},
{X86::RORX64ri, X86::RORX64mi, 0},
+ {X86::RORX64ri_EVEX, X86::RORX64mi_EVEX, 0},
{X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16},
{X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16},
{X86::ROUNDSDr, X86::ROUNDSDm, 0},
@@ -586,11 +598,17 @@ static const X86FoldTableEntry Table1[] = {
{X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16},
{X86::RSQRTSSr, X86::RSQRTSSm, 0},
{X86::SARX32rr, X86::SARX32rm, 0},
+ {X86::SARX32rr_EVEX, X86::SARX32rm_EVEX, 0},
{X86::SARX64rr, X86::SARX64rm, 0},
+ {X86::SARX64rr_EVEX, X86::SARX64rm_EVEX, 0},
{X86::SHLX32rr, X86::SHLX32rm, 0},
+ {X86::SHLX32rr_EVEX, X86::SHLX32rm_EVEX, 0},
{X86::SHLX64rr, X86::SHLX64rm, 0},
+ {X86::SHLX64rr_EVEX, X86::SHLX64rm_EVEX, 0},
{X86::SHRX32rr, X86::SHRX32rm, 0},
+ {X86::SHRX32rr_EVEX, X86::SHRX32rm_EVEX, 0},
{X86::SHRX64rr, X86::SHRX64rm, 0},
+ {X86::SHRX64rr_EVEX, X86::SHRX64rm_EVEX, 0},
{X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16},
{X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16},
{X86::SQRTSDr, X86::SQRTSDm, 0},
@@ -1328,7 +1346,9 @@ static const X86FoldTableEntry Table2[] = {
{X86::AND64rr, X86::AND64rm, 0},
{X86::AND8rr, X86::AND8rm, 0},
{X86::ANDN32rr, X86::ANDN32rm, 0},
+ {X86::ANDN32rr_EVEX, X86::ANDN32rm_EVEX, 0},
{X86::ANDN64rr, X86::ANDN64rm, 0},
+ {X86::ANDN64rr_EVEX, X86::ANDN64rm_EVEX, 0},
{X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16},
{X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16},
{X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16},
@@ -1475,7 +1495,9 @@ static const X86FoldTableEntry Table2[] = {
{X86::MULSSrr, X86::MULSSrm, 0},
{X86::MULSSrr_Int, X86::MULSSrm_Int, TB_NO_REVERSE},
{X86::MULX32rr, X86::MULX32rm, 0},
+ {X86::MULX32rr_EVEX, X86::MULX32rm_EVEX, 0},
{X86::MULX64rr, X86::MULX64rm, 0},
+ {X86::MULX64rr_EVEX, X86::MULX64rm_EVEX, 0},
{X86::OR16rr, X86::OR16rm, 0},
{X86::OR32rr, X86::OR32rm, 0},
{X86::OR64rr, X86::OR64rm, 0},
@@ -1512,9 +1534,13 @@ static const X86FoldTableEntry Table2[] = {
{X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16},
{X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16},
{X86::PDEP32rr, X86::PDEP32rm, 0},
+ {X86::PDEP32rr_EVEX, X86::PDEP32rm_EVEX, 0},
{X86::PDEP64rr, X86::PDEP64rm, 0},
+ {X86::PDEP64rr_EVEX, X86::PDEP64rm_EVEX, 0},
{X86::PEXT32rr, X86::PEXT32rm, 0},
+ {X86::PEXT32rr_EVEX, X86::PEXT32rm_EVEX, 0},
{X86::PEXT64rr, X86::PEXT64rm, 0},
+ {X86::PEXT64rr_EVEX, X86::PEXT64rm_EVEX, 0},
{X86::PFACCrr, X86::PFACCrm, 0},
{X86::PFADDrr, X86::PFADDrm, 0},
{X86::PFCMPEQrr, X86::PFCMPEQrm, 0},
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