[llvm] [GlobalISel] Remove dead VRegs after instruction selection (PR #73892)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 18:59:25 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-backend-x86
Author: Evgenii Kudriashov (e-kud)
<details>
<summary>Changes</summary>
Such VRegs may appear almost at all stages of the GlobalISel pipeline. These VRegs will not obtain a RegClass because it is assigned during instruction selection but since we don't have any uses, these VRegs remain without a class. Such representation is not valid in terms of MIR.
We swap dead VRegs with alive VRegs from the end of VRegs range. So, we are able to shrink all the structures from the end.
---
Patch is 66.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73892.diff
24 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineRegisterInfo.h (+5)
- (modified) llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp (+3)
- (modified) llvm/lib/CodeGen/MachineRegisterInfo.cpp (+35)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll (+48-48)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir (+1-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir (+2-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir (+8-8)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir (+8-8)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select.mir (+3-4)
- (modified) llvm/test/CodeGen/AArch64/fexplog.ll (+75-70)
- (modified) llvm/test/CodeGen/AArch64/fpow.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/frem.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/fsincos.ll (+30-28)
- (modified) llvm/test/CodeGen/AArch64/itofp.ll (+24-24)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-inc.mir (+3-5)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir (+6-6)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir (+4-4)
- (modified) llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll (+6-6)
- (modified) llvm/test/DebugInfo/AArch64/debug-reg-bank.ll (+1-1)
- (modified) llvm/test/DebugInfo/X86/debug-reg-bank.ll (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 9bca74a1d4fc82f..01190195c987dd7 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -788,6 +788,11 @@ class MachineRegisterInfo {
/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
void clearVirtRegs();
+ /// clearDeadVirtRegs - Remove virtual registers without a definition and uses.
+ /// Since virtual registers are linear and can be removed only from the end,
+ /// register ids will be shuffled.
+ void clearDeadVirtRegs();
+
/// setRegAllocationHint - Specify a register allocation hint for the
/// specified virtual register. This is typically used by target, and in case
/// of an earlier hint it will be overwritten.
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index baea773cf528e92..072722c2034c091 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -326,6 +326,9 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
// types after us (otherwise MIRPrinter would need them). Make sure the types
// disappear.
MRI.clearVirtRegTypes();
+ // We need to remove dead virtual registers as no register class has been
+ // assigned to them.
+ MRI.clearDeadVirtRegs();
// FIXME: Should we accurately track changes?
return true;
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 087604af6a71846..25e84dc6cc656b2 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -214,6 +214,41 @@ void MachineRegisterInfo::clearVirtRegs() {
I.second = 0;
}
+void MachineRegisterInfo::clearDeadVirtRegs() {
+ unsigned i = 0;
+ for (unsigned e = getNumVirtRegs(), j = e - 1; i < e; ++i) {
+ Register DeadReg = Register::index2VirtReg(i);
+ if (!reg_empty(DeadReg))
+ continue;
+
+ Register AliveReg;
+ for (; i < j; --j) {
+ AliveReg = Register::index2VirtReg(j);
+ if (!reg_empty(AliveReg))
+ break;
+ }
+ if (i == j)
+ break;
+
+ setRegClass(DeadReg, getRegClass(AliveReg));
+
+ RegAllocHints[DeadReg] = RegAllocHints[AliveReg];
+
+ if (VReg2Name.inBounds(DeadReg)) {
+ VRegNames.erase(VReg2Name[DeadReg]);
+ VReg2Name[DeadReg] = getVRegName(AliveReg);
+ }
+
+ replaceRegWith(AliveReg, DeadReg);
+ }
+ unsigned NewSize = i;
+ if (VReg2Name.size() > NewSize)
+ VReg2Name.resize(NewSize);
+
+ VRegInfo.resize(NewSize);
+ RegAllocHints.resize(NewSize);
+}
+
void MachineRegisterInfo::verifyUseList(Register Reg) const {
#ifndef NDEBUG
bool Valid = true;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
index a3d8531f5c76593..cf9768ea1b22e9e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -9,22 +9,22 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-LLSC-O1-LABEL: val_compare_and_swap:
; CHECK-LLSC-O1: // %bb.0:
; CHECK-LLSC-O1-NEXT: .LBB0_1: // =>This Inner Loop Header: Depth=1
-; CHECK-LLSC-O1-NEXT: ldaxp x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cmp x8, x2
-; CHECK-LLSC-O1-NEXT: cset w10, ne
-; CHECK-LLSC-O1-NEXT: cmp x9, x3
-; CHECK-LLSC-O1-NEXT: cinc w10, w10, ne
-; CHECK-LLSC-O1-NEXT: cbz w10, .LBB0_3
+; CHECK-LLSC-O1-NEXT: ldaxp x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cmp x9, x2
+; CHECK-LLSC-O1-NEXT: cset w8, ne
+; CHECK-LLSC-O1-NEXT: cmp x10, x3
+; CHECK-LLSC-O1-NEXT: cinc w8, w8, ne
+; CHECK-LLSC-O1-NEXT: cbz w8, .LBB0_3
; CHECK-LLSC-O1-NEXT: // %bb.2: // in Loop: Header=BB0_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stxp w10, x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB0_1
+; CHECK-LLSC-O1-NEXT: stxp w8, x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB0_1
; CHECK-LLSC-O1-NEXT: b .LBB0_4
; CHECK-LLSC-O1-NEXT: .LBB0_3: // in Loop: Header=BB0_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stxp w10, x4, x5, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB0_1
+; CHECK-LLSC-O1-NEXT: stxp w8, x4, x5, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB0_1
; CHECK-LLSC-O1-NEXT: .LBB0_4:
-; CHECK-LLSC-O1-NEXT: mov v0.d[0], x8
-; CHECK-LLSC-O1-NEXT: mov v0.d[1], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[0], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[1], x10
; CHECK-LLSC-O1-NEXT: str q0, [x0]
; CHECK-LLSC-O1-NEXT: ret
;
@@ -94,22 +94,22 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-LLSC-O1-LABEL: val_compare_and_swap_monotonic_seqcst:
; CHECK-LLSC-O1: // %bb.0:
; CHECK-LLSC-O1-NEXT: .LBB1_1: // =>This Inner Loop Header: Depth=1
-; CHECK-LLSC-O1-NEXT: ldaxp x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cmp x8, x2
-; CHECK-LLSC-O1-NEXT: cset w10, ne
-; CHECK-LLSC-O1-NEXT: cmp x9, x3
-; CHECK-LLSC-O1-NEXT: cinc w10, w10, ne
-; CHECK-LLSC-O1-NEXT: cbz w10, .LBB1_3
+; CHECK-LLSC-O1-NEXT: ldaxp x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cmp x9, x2
+; CHECK-LLSC-O1-NEXT: cset w8, ne
+; CHECK-LLSC-O1-NEXT: cmp x10, x3
+; CHECK-LLSC-O1-NEXT: cinc w8, w8, ne
+; CHECK-LLSC-O1-NEXT: cbz w8, .LBB1_3
; CHECK-LLSC-O1-NEXT: // %bb.2: // in Loop: Header=BB1_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stlxp w10, x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB1_1
+; CHECK-LLSC-O1-NEXT: stlxp w8, x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB1_1
; CHECK-LLSC-O1-NEXT: b .LBB1_4
; CHECK-LLSC-O1-NEXT: .LBB1_3: // in Loop: Header=BB1_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stlxp w10, x4, x5, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB1_1
+; CHECK-LLSC-O1-NEXT: stlxp w8, x4, x5, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB1_1
; CHECK-LLSC-O1-NEXT: .LBB1_4:
-; CHECK-LLSC-O1-NEXT: mov v0.d[0], x8
-; CHECK-LLSC-O1-NEXT: mov v0.d[1], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[0], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[1], x10
; CHECK-LLSC-O1-NEXT: str q0, [x0]
; CHECK-LLSC-O1-NEXT: ret
;
@@ -179,22 +179,22 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-LLSC-O1-LABEL: val_compare_and_swap_release_acquire:
; CHECK-LLSC-O1: // %bb.0:
; CHECK-LLSC-O1-NEXT: .LBB2_1: // =>This Inner Loop Header: Depth=1
-; CHECK-LLSC-O1-NEXT: ldaxp x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cmp x8, x2
-; CHECK-LLSC-O1-NEXT: cset w10, ne
-; CHECK-LLSC-O1-NEXT: cmp x9, x3
-; CHECK-LLSC-O1-NEXT: cinc w10, w10, ne
-; CHECK-LLSC-O1-NEXT: cbz w10, .LBB2_3
+; CHECK-LLSC-O1-NEXT: ldaxp x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cmp x9, x2
+; CHECK-LLSC-O1-NEXT: cset w8, ne
+; CHECK-LLSC-O1-NEXT: cmp x10, x3
+; CHECK-LLSC-O1-NEXT: cinc w8, w8, ne
+; CHECK-LLSC-O1-NEXT: cbz w8, .LBB2_3
; CHECK-LLSC-O1-NEXT: // %bb.2: // in Loop: Header=BB2_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stlxp w10, x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB2_1
+; CHECK-LLSC-O1-NEXT: stlxp w8, x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB2_1
; CHECK-LLSC-O1-NEXT: b .LBB2_4
; CHECK-LLSC-O1-NEXT: .LBB2_3: // in Loop: Header=BB2_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stlxp w10, x4, x5, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB2_1
+; CHECK-LLSC-O1-NEXT: stlxp w8, x4, x5, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB2_1
; CHECK-LLSC-O1-NEXT: .LBB2_4:
-; CHECK-LLSC-O1-NEXT: mov v0.d[0], x8
-; CHECK-LLSC-O1-NEXT: mov v0.d[1], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[0], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[1], x10
; CHECK-LLSC-O1-NEXT: str q0, [x0]
; CHECK-LLSC-O1-NEXT: ret
;
@@ -264,22 +264,22 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-LLSC-O1-LABEL: val_compare_and_swap_monotonic:
; CHECK-LLSC-O1: // %bb.0:
; CHECK-LLSC-O1-NEXT: .LBB3_1: // =>This Inner Loop Header: Depth=1
-; CHECK-LLSC-O1-NEXT: ldaxp x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cmp x8, x2
-; CHECK-LLSC-O1-NEXT: cset w10, ne
-; CHECK-LLSC-O1-NEXT: cmp x9, x3
-; CHECK-LLSC-O1-NEXT: cinc w10, w10, ne
-; CHECK-LLSC-O1-NEXT: cbz w10, .LBB3_3
+; CHECK-LLSC-O1-NEXT: ldaxp x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cmp x9, x2
+; CHECK-LLSC-O1-NEXT: cset w8, ne
+; CHECK-LLSC-O1-NEXT: cmp x10, x3
+; CHECK-LLSC-O1-NEXT: cinc w8, w8, ne
+; CHECK-LLSC-O1-NEXT: cbz w8, .LBB3_3
; CHECK-LLSC-O1-NEXT: // %bb.2: // in Loop: Header=BB3_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stlxp w10, x8, x9, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB3_1
+; CHECK-LLSC-O1-NEXT: stlxp w8, x9, x10, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB3_1
; CHECK-LLSC-O1-NEXT: b .LBB3_4
; CHECK-LLSC-O1-NEXT: .LBB3_3: // in Loop: Header=BB3_1 Depth=1
-; CHECK-LLSC-O1-NEXT: stlxp w10, x4, x5, [x0]
-; CHECK-LLSC-O1-NEXT: cbnz w10, .LBB3_1
+; CHECK-LLSC-O1-NEXT: stlxp w8, x4, x5, [x0]
+; CHECK-LLSC-O1-NEXT: cbnz w8, .LBB3_1
; CHECK-LLSC-O1-NEXT: .LBB3_4:
-; CHECK-LLSC-O1-NEXT: mov v0.d[0], x8
-; CHECK-LLSC-O1-NEXT: mov v0.d[1], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[0], x9
+; CHECK-LLSC-O1-NEXT: mov v0.d[1], x10
; CHECK-LLSC-O1-NEXT: str q0, [x0]
; CHECK-LLSC-O1-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
index a7d7a1e81617e4f..05e45f680e328b5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
@@ -26,14 +26,14 @@ define i32 @test(i32 %a, i1 %c) {
; TRANSLATED-NEXT: G_BR %bb.2
; TRANSLATED-NEXT: {{ $}}
; TRANSLATED-NEXT: bb.2.common.ret:
- ; TRANSLATED-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.3, [[C1]](s32), %bb.1
+ ; TRANSLATED-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD:%[0-9]+]](s32), %bb.3, [[C1]](s32), %bb.1
; TRANSLATED-NEXT: $w0 = COPY [[PHI]](s32)
; TRANSLATED-NEXT: RET_ReallyLR implicit $w0
; TRANSLATED-NEXT: {{ $}}
; TRANSLATED-NEXT: bb.3.cont:
; TRANSLATED-NEXT: successors: %bb.2(0x80000000)
; TRANSLATED-NEXT: {{ $}}
- ; TRANSLATED-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
+ ; TRANSLATED-NEXT: [[ADD]]:_(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
; TRANSLATED-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; TRANSLATED-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; TRANSLATED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -58,14 +58,14 @@ define i32 @test(i32 %a, i1 %c) {
; PRESELECTION-NEXT: G_BR %bb.2
; PRESELECTION-NEXT: {{ $}}
; PRESELECTION-NEXT: bb.2.common.ret:
- ; PRESELECTION-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI %7(s32), %bb.3, [[C]](s32), %bb.1
+ ; PRESELECTION-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[ADD:%[0-9]+]](s32), %bb.3, [[C]](s32), %bb.1
; PRESELECTION-NEXT: $w0 = COPY [[PHI]](s32)
; PRESELECTION-NEXT: RET_ReallyLR implicit $w0
; PRESELECTION-NEXT: {{ $}}
; PRESELECTION-NEXT: bb.3.cont:
; PRESELECTION-NEXT: successors: %bb.2(0x80000000)
; PRESELECTION-NEXT: {{ $}}
- ; PRESELECTION-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
+ ; PRESELECTION-NEXT: [[ADD]]:gpr(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
; PRESELECTION-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; PRESELECTION-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; PRESELECTION-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -84,14 +84,14 @@ define i32 @test(i32 %a, i1 %c) {
; POSTSELECTION-NEXT: B %bb.2
; POSTSELECTION-NEXT: {{ $}}
; POSTSELECTION-NEXT: bb.2.common.ret:
- ; POSTSELECTION-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI %7, %bb.3, [[COPY2]], %bb.1
+ ; POSTSELECTION-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[ADDWrr:%[0-9]+]], %bb.3, [[COPY2]], %bb.1
; POSTSELECTION-NEXT: $w0 = COPY [[PHI]]
; POSTSELECTION-NEXT: RET_ReallyLR implicit $w0
; POSTSELECTION-NEXT: {{ $}}
; POSTSELECTION-NEXT: bb.3.cont:
; POSTSELECTION-NEXT: successors: %bb.2(0x80000000)
; POSTSELECTION-NEXT: {{ $}}
- ; POSTSELECTION-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[MOVi32imm]]
+ ; POSTSELECTION-NEXT: [[ADDWrr]]:gpr32 = ADDWrr [[COPY]], [[MOVi32imm]]
; POSTSELECTION-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; POSTSELECTION-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; POSTSELECTION-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
index e47411b7b178a8e..6fc216b686042ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
@@ -37,7 +37,7 @@ registers:
# CHECK: body:
# CHECK: bb.0:
-# CHECK: TBNZW %1, 0, %bb.1
+# CHECK: TBNZW %{{[0-9]+}}, 0, %bb.1
# CHECK: B %bb.0
body: |
bb.0:
@@ -60,7 +60,7 @@ registers:
# CHECK: body:
# CHECK: bb.0:
-# CHECK: %0:gpr64 = COPY $x0
+# CHECK: %{{[0-9]+}}:gpr64 = COPY $x0
# CHECK: BR %0
body: |
bb.0:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
index e015d35916ac3d0..a4ecf8c16613c58 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
@@ -65,7 +65,7 @@ body: |
; CHECK-LABEL: name: test_dbg_value_dead
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: DBG_VALUE %1:gpr64, $noreg, !7, !DIExpression(), debug-location !9
+ ; CHECK-NEXT: DBG_VALUE %{{[0-9]+}}:gpr64, $noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_ZEXT %0:gpr(s32)
DBG_VALUE %1(s64), $noreg, !7, !DIExpression(), debug-location !9
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
index 231785355c83230..ab962a6a47aef8d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
@@ -13,8 +13,7 @@ name: hint
legalized: true
regBankSelected: true
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
+# CHECK: registers: []
registers:
- { id: 0, class: gpr }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
index afc5ea2e64b7e1d..3255e8529c248a8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
@@ -70,9 +70,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
- ; CHECK-NEXT: early-clobber %17:gpr64, early-clobber %18:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
+ ; CHECK-NEXT: early-clobber [[BADDR:%[0-9]+]]:gpr64, early-clobber %{{[0-9]+}}:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
; CHECK-NEXT: JUMP_TABLE_DEBUG_INFO 0
- ; CHECK-NEXT: BR %17
+ ; CHECK-NEXT: BR [[BADDR]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb:
; CHECK-NEXT: successors: %bb.4(0x80000000)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
index 2145ba308664484..764aecc7285d181 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
@@ -55,7 +55,7 @@ legalized: true
regBankSelected: true
# CHECK: body:
-# CHECK: %2:gpr64sp = ANDXri %0, 8060
+# CHECK: %1:gpr64sp = ANDXri %0, 8060
body: |
bb.0:
liveins: $x0
@@ -203,9 +203,8 @@ tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
index 6b899dc4c84abb6..5a2d941dabfe6ed 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
@@ -27,8 +27,8 @@ body: |
; CHECK: liveins: $w0, $x1, $x2
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
- ; CHECK: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
- ; CHECK: $w0 = COPY %2
+ ; CHECK: early-clobber [[STATUS:%[0-9]+]]:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
+ ; CHECK: $w0 = COPY [[STATUS]]
; CHECK: RET_ReallyLR implicit $w0
%1:gpr(s64) = COPY $x1
%2:gpr(p0) = COPY $x2
@@ -50,8 +50,8 @@ body: |
; CHECK: liveins: $w0, $w1, $x2
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
- ; CHECK: early-clobber %3:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
- ; CHECK: $w0 = COPY %3
+ ; CHECK: early-clobber [[STATUS:%[0-9]+]]:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
+ ; CHECK: $w0 = COPY [[STATUS]]
; CHECK: RET_ReallyLR implicit $w0
%1:gpr(s32) = COPY $w1
%2:gpr(p0) = COPY $x2
@@ -78,8 +78,8 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
- ; CHECK: $w0 = COPY %5
+ ; CHECK: early-clobber [[STATUS:%[0-9]+]]:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
+ ; CHECK: $w0 = COPY [[STATUS]]
; CHECK: RET_ReallyLR implicit $w0
%3:gpr(s32) = COPY $w1
%2:gpr(p0) = COPY $x2
@@ -108,8 +108,8 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
- ; CHECK: $w0 = COPY %5
+ ; CHECK: early-clobber [[STATUS:%[0-9]+]]:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
+ ; CHECK: $w0 = COPY [[STATUS]]
; CHECK: RET_ReallyLR implicit $w0
%3:gpr(s32) = COPY $w1
%2:gpr(p0) = COPY $x2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
index ebbf69e51ee8105..d5a2cbf2a799ee2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
@@ -25,8 +25,8 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
- ; CHECK: $w0 = COPY %5
+ ; CHECK: early-clobber [[STATUS:%[0-9]+]]:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
+ ; CHECK...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/73892
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