[llvm] Optimize (shift x (and y, BitWidth - 1)) to (shift x, y) (PR #73889)
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Wed Nov 29 18:33:15 PST 2023
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff 246b8eae20564e2c34690803efdbaa9cec7c90a1 a7782e84e816d84ec1032f66f968b8b9ff772bb1 -- llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/lib/Target/Mips/MipsISelDAGToDAG.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 2c819b6c2a..12b35a0e43 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -32,8 +32,8 @@
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/KnownBits.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
@@ -327,12 +327,16 @@ bool MipsDAGToDAGISel::SelectInlineAsmMemoryOperand(
}
bool MipsDAGToDAGISel::isUnneededShiftMask(SDNode *N,
- unsigned ShAmtBits) const {
+ unsigned ShAmtBits) const {
assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
const APInt &RHS = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
if (RHS.countr_one() >= ShAmtBits) {
- LLVM_DEBUG(dbgs() << DEBUG_TYPE << " Need optimize 'and & shl/srl/sra' and operand value bits is " << RHS.countr_one() << "\n");
+ LLVM_DEBUG(
+ dbgs()
+ << DEBUG_TYPE
+ << " Need optimize 'and & shl/srl/sra' and operand value bits is "
+ << RHS.countr_one() << "\n");
return true;
}
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
index 7136f691d2..52207d0f62 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -144,7 +144,6 @@ private:
InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const;
-
};
}
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https://github.com/llvm/llvm-project/pull/73889
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