[llvm] MachineVerifier: Reject extra non-register operands on instructions (PR #73758)

[Matt Arsenault via llvm-commits]

================
@@ -231,10 +231,6 @@ void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
   // OpNo now points as the desired insertion point.  Unless this is a variadic
   // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
   // RegMask operands go between the explicit and implicit operands.
-  assert((MCID->isVariadic() || OpNo < MCID->getNumOperands() ||
-          Op.isValidExcessOperand()) &&
-         "Trying to add an operand to a machine instr that is already done!");
-
----------------
arsenm wrote:

Preserving it would require inventing a mechanism to bypass it for the parser case, otherwise we have to repeat operand checks there and the verifier, and the verifier is no longer testable. This is also more restrictive if you are mutating an instruction in place 

https://github.com/llvm/llvm-project/pull/73758