[llvm] e3021bd - [RISCV] Add RISCVISD::SLLW to computeKnownBitsForTargetNode.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-29T16:21:43-08:00
New Revision: e3021bdecde584c48bfd43ce4991ab7762751f09

URL: https://github.com/llvm/llvm-project/commit/e3021bdecde584c48bfd43ce4991ab7762751f09
DIFF: https://github.com/llvm/llvm-project/commit/e3021bdecde584c48bfd43ce4991ab7762751f09.diff

LOG: [RISCV] Add RISCVISD::SLLW to computeKnownBitsForTargetNode.

Found while investigating whether we still need to stop DAG combiner
from turning (i64 (sext (i32 X))) into zext when i32 is known non
negative.

No test case because I still need to find fixes for some other issues
before I can remove the code from DAGCombiner.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 18c6ca5348b6213..14f51c5259ebba4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15812,6 +15812,15 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known = Known.sext(BitWidth);
     break;
   }
+  case RISCVISD::SLLW: {
+    KnownBits Known2;
+    Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    Known = KnownBits::shl(Known.trunc(32), Known2.trunc(5).zext(32));
+    // Restore the original width by sign extending.
+    Known = Known.sext(BitWidth);
+    break;
+  }
   case RISCVISD::CTZW: {
     KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
     unsigned PossibleTZ = Known2.trunc(32).countMaxTrailingZeros();