[llvm] [AArch64] Pass scratch regs as operands to StoreSwiftAsyncContext. (PR #73332)

[Ahmed Bougacha via llvm-commits]

https://github.com/ahmedbougacha requested changes to this pull request.

Hmm, this may be a little tricky: x16/x17 are special here, because they're the only GPRs that have some platform-provided security guarantees (they're signed when saved on context switches), which we care about whenever we do a PAC sign.

In this case that's maybe not all that meaningful though, in part because the security guarantees are more about the kernel, where we don't have this sort of codegen today, and in part because we're just feeding the PAC from x22 anyway on one side (though on the other, SP is safe to derive discriminators from.)

But at the end of the day I don't know that we have a much better way to fix this (that wouldn't involve wiring a bunch of stuff through shrink wrapping and/or PEI?)  I'll think about it a little bit more.

In the meantime, let me know if you think of a simple alternative that would try harder to keep this in x16/x17, so that we don't have to prove that it's always okay if it's in other GPRs ;)

https://github.com/llvm/llvm-project/pull/73332