[llvm] 738c3ed - [RISCV] Pre-commit test for FrameIndex handling in getMemOperandsWithOffsetWidth

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2023-11-29T14:51:27Z
New Revision: 738c3ede315acb413fc8e0e15c78657102110e94

URL: https://github.com/llvm/llvm-project/commit/738c3ede315acb413fc8e0e15c78657102110e94
DIFF: https://github.com/llvm/llvm-project/commit/738c3ede315acb413fc8e0e15c78657102110e94.diff

LOG: [RISCV] Pre-commit test for FrameIndex handling in getMemOperandsWithOffsetWidth

Currently AArch64 handles a FrameIndex operand in this function, but we
fail to.

Added: 
    

Modified: 
    llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 43e98d703d7a33aa..135d7dbb426e3c29 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -153,6 +153,19 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
            .addImm(16);
   Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
                                            OffsetIsScalable, Width, TRI);
+
+  // TODO: AArch64 can handle this case, and we probably should too.
+  BaseOps.clear();
+  MMO = MF->getMachineMemOperand(MachinePointerInfo(),
+                                 MachineMemOperand::MOStore, 4, Align(4));
+  MI = BuildMI(*MF, DL, TII->get(RISCV::SW))
+           .addReg(RISCV::X3)
+           .addFrameIndex(2)
+           .addImm(4)
+           .addMemOperand(MMO);
+  Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
+                                           OffsetIsScalable, Width, TRI);
+  EXPECT_FALSE(Res);
 }
 
 } // namespace