[llvm] MachineVerifier: Reject extra non-register operands on instructions (PR #73758)

[via llvm-commits]

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@@ -231,10 +231,6 @@ void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
   // OpNo now points as the desired insertion point.  Unless this is a variadic
   // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
   // RegMask operands go between the explicit and implicit operands.
-  assert((MCID->isVariadic() || OpNo < MCID->getNumOperands() ||
-          Op.isValidExcessOperand()) &&
-         "Trying to add an operand to a machine instr that is already done!");
-
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qcolombet wrote:

I feel that assert still has value to actually catch when we screw up the operation creation.

https://github.com/llvm/llvm-project/pull/73758