[llvm] [NVPTX] Lower 16xi8 and 8xi8 stores efficiently (PR #73646)

[via llvm-commits]

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@@ -5557,6 +5557,50 @@ static SDValue PerformLOADCombine(SDNode *N,
       DL);
 }
 
+// Lower a v16i8 (or a v8i8) store into a StoreV4 operation with i32 results
+// instead of letting ReplaceLoadVector split it into smaller stores during
+// legalization. This is done at dag-combine1 time, so that vector operations
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ldrumm wrote:

My mistake; I read it as a typo

https://github.com/llvm/llvm-project/pull/73646