[llvm] 6cf3566 - [NFC][MachineScheduler] Rename NumLoads parameter of shouldClusterMemOps to ClusterSize (#73757)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 01:47:07 PST 2023
Author: Alex Bradbury
Date: 2023-11-29T09:47:03Z
New Revision: 6cf3566850a807085d413dee4a573b3eca7b6bee
URL: https://github.com/llvm/llvm-project/commit/6cf3566850a807085d413dee4a573b3eca7b6bee
DIFF: https://github.com/llvm/llvm-project/commit/6cf3566850a807085d413dee4a573b3eca7b6bee.diff
LOG: [NFC][MachineScheduler] Rename NumLoads parameter of shouldClusterMemOps to ClusterSize (#73757)
As the same hook is called for both load and store clustering, NumLoads
is a misleading name. Use ClusterSize instead.
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index de065849eaa6ebc..665b7449ddb820a 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1496,13 +1496,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// to TargetPassConfig::createMachineScheduler() to have an effect.
///
/// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
- /// \p NumLoads is the number of loads that will be in the cluster if this
- /// hook returns true.
+ /// \p ClusterSize is the number of operations in the resulting load/store
+ /// cluster if this hook returns true.
/// \p NumBytes is the number of bytes that will be loaded from all the
/// clustered loads if this hook returns true.
virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
ArrayRef<const MachineOperand *> BaseOps2,
- unsigned NumLoads, unsigned NumBytes) const {
+ unsigned ClusterSize,
+ unsigned NumBytes) const {
llvm_unreachable("target did not implement shouldClusterMemOps()");
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a95ab3c7e0f288a..e97f17e3f49c587 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4231,7 +4231,7 @@ static bool shouldClusterFI(const MachineFrameInfo &MFI, int FI1,
/// Only called for LdSt for which getMemOperandWithOffset returns true.
bool AArch64InstrInfo::shouldClusterMemOps(
ArrayRef<const MachineOperand *> BaseOps1,
- ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads,
+ ArrayRef<const MachineOperand *> BaseOps2, unsigned ClusterSize,
unsigned NumBytes) const {
assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
const MachineOperand &BaseOp1 = *BaseOps1.front();
@@ -4249,7 +4249,7 @@ bool AArch64InstrInfo::shouldClusterMemOps(
return false;
// Only cluster up to a single pair.
- if (NumLoads > 2)
+ if (ClusterSize > 2)
return false;
if (!isPairableLdStInst(FirstLdSt) || !isPairableLdStInst(SecondLdSt))
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index a934103c90cbf92..cc588cdad6b8e5a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -180,7 +180,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
ArrayRef<const MachineOperand *> BaseOps2,
- unsigned NumLoads, unsigned NumBytes) const override;
+ unsigned ClusterSize,
+ unsigned NumBytes) const override;
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 328bc66f46d863a..b5b456d6912544f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -542,7 +542,7 @@ static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
ArrayRef<const MachineOperand *> BaseOps2,
- unsigned NumLoads,
+ unsigned ClusterSize,
unsigned NumBytes) const {
// If the mem ops (to be clustered) do not have the same base ptr, then they
// should not be clustered
@@ -568,8 +568,8 @@ bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
// (3) 9 <= LoadSize <= 12: cluster at max 2 mem ops
// (4) 13 <= LoadSize <= 16: cluster at max 2 mem ops
// (5) LoadSize >= 17: do not cluster
- const unsigned LoadSize = NumBytes / NumLoads;
- const unsigned NumDWORDs = ((LoadSize + 3) / 4) * NumLoads;
+ const unsigned LoadSize = NumBytes / ClusterSize;
+ const unsigned NumDWORDs = ((LoadSize + 3) / 4) * ClusterSize;
return NumDWORDs <= 8;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index de2820e5c013ee3..eba817756e9c58e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -235,7 +235,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
ArrayRef<const MachineOperand *> BaseOps2,
- unsigned NumLoads, unsigned NumBytes) const override;
+ unsigned ClusterSize,
+ unsigned NumBytes) const override;
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
int64_t Offset1, unsigned NumLoads) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index c9c7dc886253c39..6784049348b1638 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2879,7 +2879,7 @@ static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc,
bool PPCInstrInfo::shouldClusterMemOps(
ArrayRef<const MachineOperand *> BaseOps1,
- ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads,
+ ArrayRef<const MachineOperand *> BaseOps2, unsigned ClusterSize,
unsigned NumBytes) const {
assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
@@ -2888,9 +2888,10 @@ bool PPCInstrInfo::shouldClusterMemOps(
assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
"Only base registers and frame indices are supported.");
- // The NumLoads means the number of loads that has been clustered.
+ // ClusterSize means the number of memory operations that will have been
+ // clustered if this hook returns true.
// Don't cluster memory op if there are already two ops clustered at least.
- if (NumLoads > 2)
+ if (ClusterSize > 2)
return false;
// Cluster the load/store only when they have the same base
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index eb480916679e9a9..31e9859a41739a1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -531,7 +531,8 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// adjacent.
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
ArrayRef<const MachineOperand *> BaseOps2,
- unsigned NumLoads, unsigned NumBytes) const override;
+ unsigned ClusterSize,
+ unsigned NumBytes) const override;
/// Return true if two MIs access
diff erent memory addresses and false
/// otherwise
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