[llvm] 35db35b - [RISCV][GISel] Support G_FCOPYSIGN with F and D extension.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 21:56:31 PST 2023
Author: Craig Topper
Date: 2023-11-28T21:50:04-08:00
New Revision: 35db35b7cfb80139ab6f23c7f10c47df5d1d7462
URL: https://github.com/llvm/llvm-project/commit/35db35b7cfb80139ab6f23c7f10c47df5d1d7462
DIFF: https://github.com/llvm/llvm-project/commit/35db35b7cfb80139ab6f23c7f10c47df5d1d7462.diff
LOG: [RISCV][GISel] Support G_FCOPYSIGN with F and D extension.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 0a73681acca27fe..8905aa77dfcdd75 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -254,6 +254,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM})
.legalIf(typeIsScalarFPArith(0, ST));
+ getActionDefinitionsBuilder(G_FCOPYSIGN)
+ .legalIf(all(typeIsScalarFPArith(0, ST), typeIsScalarFPArith(1, ST)));
+
getActionDefinitionsBuilder(G_FPTRUNC).legalIf(
[=, &ST](const LegalityQuery &Query) -> bool {
return (ST.hasStdExtD() && typeIs(0, s32)(Query) &&
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index a5e453fa5821e5c..e28bd50b20d8315 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -141,6 +141,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
case TargetOpcode::G_FFLOOR:
case TargetOpcode::G_FNEARBYINT:
case TargetOpcode::G_FNEG:
+ case TargetOpcode::G_FCOPYSIGN:
case TargetOpcode::G_FCOS:
case TargetOpcode::G_FSIN:
case TargetOpcode::G_FLOG10:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
index 865ade4f3170cfd..78bb91d2eb275ed 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
@@ -263,6 +263,30 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
+...
+---
+name: fcopysign_f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fcopysign_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
+ ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:fprb(s32) = COPY $f10_f
+ %1:fprb(s32) = COPY $f11_f
+ %2:fprb(s32) = G_FCOPYSIGN %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fsub_f64
@@ -476,3 +500,27 @@ body: |
PseudoRET implicit $f10_d
...
+---
+name: fcopysign_f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fcopysign_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+ ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:fprb(s64) = COPY $f10_d
+ %1:fprb(s64) = COPY $f11_d
+ %2:fprb(s64) = G_FCOPYSIGN %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
index e7bb8dfd89daeeb..599779d09c2c151 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
@@ -209,6 +209,27 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
+...
+---
+name: fcopysign_f32
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fcopysign_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32)
+ ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = G_FCOPYSIGN %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fadd_f64
@@ -416,3 +437,24 @@ body: |
PseudoRET implicit $f10_d
...
+---
+name: fcopysign_f64
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fcopysign_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
+ ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = G_FCOPYSIGN %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
index 1933678daef7b50..1ac6837a77bdb9a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
@@ -231,6 +231,29 @@ body: |
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f
+...
+---
+name: fcopysign_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fcopysign_f32
+ ; CHECK: liveins: $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32)
+ ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(s32) = COPY $f10_f
+ %1:_(s32) = COPY $f11_f
+ %2:_(s32) = G_FCOPYSIGN %0, %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
...
---
name: fadd_f64
@@ -458,3 +481,26 @@ body: |
PseudoRET implicit $f10_d
...
+---
+name: fcopysign_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fcopysign_f64
+ ; CHECK: liveins: $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64)
+ ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(s64) = COPY $f10_d
+ %1:_(s64) = COPY $f11_d
+ %2:_(s64) = G_FCOPYSIGN %0, %1
+ $f10_d = COPY %2(s64)
+ PseudoRET implicit $f10_d
+
+...
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