[llvm] [RISCV][GISel] Move G_BRJT expansion to legalization (PR #73711)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 21:07:01 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/73711
>From faac67b9be6afbc33df4439ed2febffa22960480 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 28 Nov 2023 13:33:52 -0800
Subject: [PATCH 1/3] [RISCV][GISel] Move G_BRJT expansion to legalization
Instead of custom selecting a bunch of instructions, we can
expand to generic MIR during legalization.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 52 -----
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 61 ++++-
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 1 +
.../jump-table-brjt-medium-rv64.mir | 160 -------------
.../jump-table-brjt-pic-rv64.mir | 161 -------------
.../jump-table-brjt-rv32.mir | 213 ------------------
.../jump-table-brjt-small-rv64.mir | 161 -------------
.../CodeGen/RISCV/GlobalISel/jumptable.ll | 4 +-
.../legalize-jump-table-brjt-medium-rv64.mir | 163 ++++++++++++++
.../legalize-jump-table-brjt-pic-rv32.mir} | 84 +++----
.../legalize-jump-table-brjt-pic-rv64.mir | 165 ++++++++++++++
.../legalize-jump-table-brjt-rv32.mir | 10 +-
...> legalize-jump-table-brjt-small-rv64.mir} | 37 +--
13 files changed, 463 insertions(+), 809 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir
rename llvm/test/CodeGen/RISCV/GlobalISel/{instruction-select/jump-table-brjt-pic-rv32.mir => legalizer/legalize-jump-table-brjt-pic-rv32.mir} (56%)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir
rename llvm/test/CodeGen/RISCV/GlobalISel/legalizer/{legalize-jump-table-brjt-rv64.mir => legalize-jump-table-brjt-small-rv64.mir} (81%)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 9b4577dec87c570..c7653f882f4030b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -542,58 +542,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
MI.eraseFromParent();
return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
}
- case TargetOpcode::G_BRJT: {
- // FIXME: Move to legalization?
- const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
- unsigned EntrySize = MJTI->getEntrySize(MF.getDataLayout());
- assert((EntrySize == 4 || (Subtarget->is64Bit() && EntrySize == 8)) &&
- "Unsupported jump-table entry size");
- assert(
- (MJTI->getEntryKind() == MachineJumpTableInfo::EK_LabelDifference32 ||
- MJTI->getEntryKind() == MachineJumpTableInfo::EK_Custom32 ||
- MJTI->getEntryKind() == MachineJumpTableInfo::EK_BlockAddress) &&
- "Unexpected jump-table entry kind");
-
- auto SLL =
- MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {MI.getOperand(2)})
- .addImm(Log2_32(EntrySize));
- if (!SLL.constrainAllUses(TII, TRI, RBI))
- return false;
-
- // TODO: Use SHXADD. Moving to legalization would fix this automatically.
- auto ADD = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass},
- {MI.getOperand(0), SLL.getReg(0)});
- if (!ADD.constrainAllUses(TII, TRI, RBI))
- return false;
-
- unsigned LdOpc = EntrySize == 8 ? RISCV::LD : RISCV::LW;
- auto Dest =
- MIB.buildInstr(LdOpc, {&RISCV::GPRRegClass}, {ADD.getReg(0)})
- .addImm(0)
- .addMemOperand(MF.getMachineMemOperand(
- MachinePointerInfo::getJumpTable(MF), MachineMemOperand::MOLoad,
- EntrySize, Align(MJTI->getEntryAlignment(MF.getDataLayout()))));
- if (!Dest.constrainAllUses(TII, TRI, RBI))
- return false;
-
- // If the Kind is EK_LabelDifference32, the table stores an offset from
- // the location of the table. Add the table address to get an absolute
- // address.
- if (MJTI->getEntryKind() == MachineJumpTableInfo::EK_LabelDifference32) {
- Dest = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass},
- {Dest.getReg(0), MI.getOperand(0)});
- if (!Dest.constrainAllUses(TII, TRI, RBI))
- return false;
- }
-
- auto Branch =
- MIB.buildInstr(RISCV::PseudoBRIND, {}, {Dest.getReg(0)}).addImm(0);
- if (!Branch.constrainAllUses(TII, TRI, RBI))
- return false;
-
- MI.eraseFromParent();
- return true;
- }
case TargetOpcode::G_BRINDIRECT:
MI.setDesc(TII.get(RISCV::PseudoBRIND));
MI.addOperand(MachineOperand::CreateImm(0));
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 0a73681acca27fe..3d82a4cffbe629e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -14,6 +14,7 @@
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
@@ -179,7 +180,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder(G_BRCOND).legalFor({sXLen}).minScalar(0, sXLen);
- getActionDefinitionsBuilder(G_BRJT).legalFor({{p0, sXLen}});
+ getActionDefinitionsBuilder(G_BRJT).customFor({{p0, sXLen}});
getActionDefinitionsBuilder(G_BRINDIRECT).legalFor({p0});
@@ -317,6 +318,62 @@ bool RISCVLegalizerInfo::legalizeShlAshrLshr(
return true;
}
+bool RISCVLegalizerInfo::legalizeBRJT(MachineInstr &MI,
+ MachineIRBuilder &MIRBuilder) const {
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+ auto &MF = *MI.getParent()->getParent();
+ const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
+ unsigned EntrySize = MJTI->getEntrySize(MF.getDataLayout());
+
+ Register PtrReg = MI.getOperand(0).getReg();
+ LLT PtrTy = MRI.getType(PtrReg);
+ Register IndexReg = MI.getOperand(2).getReg();
+ LLT IndexTy = MRI.getType(IndexReg);
+
+ MachineInstrBuilder Index;
+ if (isPowerOf2_32(EntrySize)) {
+ auto ShiftAmt = MIRBuilder.buildConstant(IndexTy, Log2_32(EntrySize));
+ Index = MIRBuilder.buildShl(IndexTy, IndexReg, ShiftAmt);
+ } else
+ return false;
+
+ auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, Index);
+
+ MachineMemOperand *MMO = MF.getMachineMemOperand(
+ MachinePointerInfo::getJumpTable(MF), MachineMemOperand::MOLoad,
+ EntrySize, Align(MJTI->getEntryAlignment(MF.getDataLayout())));
+
+ Register TargetReg;
+ switch (MJTI->getEntryKind()) {
+ default:
+ llvm_unreachable("Unexpected jumptable entry kind");
+ case MachineJumpTableInfo::EK_LabelDifference32: {
+ // For PIC, the sequence is:
+ // BRIND(load(Jumptable + index) + RelocBase)
+ // RelocBase can be JumpTable, GOT or some sort of global base.
+ auto Load = MIRBuilder.buildLoadInstr(
+ TargetOpcode::G_LOAD, LLT::scalar(EntrySize * 8), Addr, *MMO);
+ Load = MIRBuilder.buildSExtOrTrunc(IndexTy, Load);
+ TargetReg = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, Load).getReg(0);
+ break;
+ }
+ case MachineJumpTableInfo::EK_Custom32: {
+ auto Load = MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, IndexTy,
+ Addr, *MMO);
+ TargetReg = MIRBuilder.buildIntToPtr(PtrTy, Load).getReg(0);
+ break;
+ }
+ case MachineJumpTableInfo::EK_BlockAddress:
+ TargetReg = MIRBuilder.buildLoad(PtrTy, Addr, *MMO).getReg(0);
+ break;
+ }
+
+ MIRBuilder.buildBrIndirect(TargetReg);
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MachineInstr &MI) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
@@ -357,6 +414,8 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MI.eraseFromParent();
return true;
}
+ case TargetOpcode::G_BRJT:
+ return legalizeBRJT(MI, MIRBuilder);
}
llvm_unreachable("expected switch to return");
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index 6a5f49cd98d1842..c2a214cde0be4bc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -35,6 +35,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
private:
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const;
+ bool legalizeBRJT(MachineInstr &MI, MachineIRBuilder &MIRBuilder) const;
};
} // end namespace llvm
#endif
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
deleted file mode 100644
index 5d980e7721458e9..000000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
+++ /dev/null
@@ -1,160 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
-# RUN: -code-model=medium | FileCheck %s
-
---- |
- define i32 @jt_test(i32 signext %in) {
- entry:
- %0 = sext i32 %in to i64
- switch i64 %0, label %default [
- i64 1, label %bb1
- i64 2, label %bb2
- i64 3, label %bb3
- i64 4, label %bb4
- i64 5, label %bb5
- i64 6, label %bb6
- ]
-
- bb1: ; preds = %entry
- ret i32 4
-
- bb2: ; preds = %entry
- ret i32 3
-
- bb3: ; preds = %entry
- ret i32 2
-
- bb4: ; preds = %entry
- ret i32 1
-
- bb5: ; preds = %entry
- ret i32 100
-
- bb6: ; preds = %entry
- ret i32 200
-
- default: ; preds = %entry
- ret i32 1000
- }
-
-...
----
-name: jt_test
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-jumpTable:
- kind: block-address
- entries:
- - id: 0
- blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
-body: |
- ; CHECK-LABEL: name: jt_test
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
- ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[ADDIW]], -1
- ; CHECK-NEXT: BLTU [[ADDI]], [[ADDI1]], %bb.8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA %jump-table.0
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI1]], 3
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLLA]], [[SLLI]]
- ; CHECK-NEXT: [[LD:%[0-9]+]]:gprjalr = LD [[ADD]], 0 :: (load (s64) from jump-table)
- ; CHECK-NEXT: PseudoBRIND [[LD]], 0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 4
- ; CHECK-NEXT: $x10 = COPY [[ADDI2]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.bb2:
- ; CHECK-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: $x10 = COPY [[ADDI3]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.bb3:
- ; CHECK-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
- ; CHECK-NEXT: $x10 = COPY [[ADDI4]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.5.bb4:
- ; CHECK-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 1
- ; CHECK-NEXT: $x10 = COPY [[ADDI5]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.6.bb5:
- ; CHECK-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 100
- ; CHECK-NEXT: $x10 = COPY [[ADDI6]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.7.bb6:
- ; CHECK-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 200
- ; CHECK-NEXT: $x10 = COPY [[ADDI7]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.8.default:
- ; CHECK-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI $x0, 1000
- ; CHECK-NEXT: $x10 = COPY [[ADDI8]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- bb.1.entry:
- successors: %bb.8, %bb.9
- liveins: $x10
-
- %1:gprb(s64) = COPY $x10
- %2:gprb(s64) = G_ASSERT_SEXT %1, 32
- %7:gprb(s64) = G_CONSTANT i64 5
- %3:gprb(s64) = G_SEXT_INREG %2, 32
- %4:gprb(s64) = G_CONSTANT i64 1
- %5:gprb(s64) = G_SUB %3, %4
- %26:gprb(s64) = G_ICMP intpred(ugt), %5(s64), %7
- G_BRCOND %26(s64), %bb.8
-
- bb.9.entry:
- successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
-
- %10:gprb(p0) = G_JUMP_TABLE %jump-table.0
- G_BRJT %10(p0), %jump-table.0, %5(s64)
-
- bb.2.bb1:
- %22:gprb(s64) = G_CONSTANT i64 4
- $x10 = COPY %22(s64)
- PseudoRET implicit $x10
-
- bb.3.bb2:
- %20:gprb(s64) = G_CONSTANT i64 3
- $x10 = COPY %20(s64)
- PseudoRET implicit $x10
-
- bb.4.bb3:
- %18:gprb(s64) = G_CONSTANT i64 2
- $x10 = COPY %18(s64)
- PseudoRET implicit $x10
-
- bb.5.bb4:
- %16:gprb(s64) = G_CONSTANT i64 1
- $x10 = COPY %16(s64)
- PseudoRET implicit $x10
-
- bb.6.bb5:
- %14:gprb(s64) = G_CONSTANT i64 100
- $x10 = COPY %14(s64)
- PseudoRET implicit $x10
-
- bb.7.bb6:
- %12:gprb(s64) = G_CONSTANT i64 200
- $x10 = COPY %12(s64)
- PseudoRET implicit $x10
-
- bb.8.default:
- %24:gprb(s64) = G_CONSTANT i64 1000
- $x10 = COPY %24(s64)
- PseudoRET implicit $x10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
deleted file mode 100644
index 77156b913c5e8b4..000000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
+++ /dev/null
@@ -1,161 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
-# RUN: -relocation-model=pic | FileCheck %s
-
---- |
- define i32 @jt_test(i32 signext %in) {
- entry:
- %0 = sext i32 %in to i64
- switch i64 %0, label %default [
- i64 1, label %bb1
- i64 2, label %bb2
- i64 3, label %bb3
- i64 4, label %bb4
- i64 5, label %bb5
- i64 6, label %bb6
- ]
-
- bb1: ; preds = %entry
- ret i32 4
-
- bb2: ; preds = %entry
- ret i32 3
-
- bb3: ; preds = %entry
- ret i32 2
-
- bb4: ; preds = %entry
- ret i32 1
-
- bb5: ; preds = %entry
- ret i32 100
-
- bb6: ; preds = %entry
- ret i32 200
-
- default: ; preds = %entry
- ret i32 1000
- }
-
-...
----
-name: jt_test
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-jumpTable:
- kind: label-difference32
- entries:
- - id: 0
- blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
-body: |
- ; CHECK-LABEL: name: jt_test
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
- ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[ADDIW]], -1
- ; CHECK-NEXT: BLTU [[ADDI]], [[ADDI1]], %bb.8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA %jump-table.0
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI1]], 2
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLLA]], [[SLLI]]
- ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[ADD]], 0 :: (load (s32) from jump-table)
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gprjalr = ADD [[LW]], [[PseudoLLA]]
- ; CHECK-NEXT: PseudoBRIND [[ADD1]], 0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 4
- ; CHECK-NEXT: $x10 = COPY [[ADDI2]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.bb2:
- ; CHECK-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: $x10 = COPY [[ADDI3]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.bb3:
- ; CHECK-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
- ; CHECK-NEXT: $x10 = COPY [[ADDI4]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.5.bb4:
- ; CHECK-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 1
- ; CHECK-NEXT: $x10 = COPY [[ADDI5]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.6.bb5:
- ; CHECK-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 100
- ; CHECK-NEXT: $x10 = COPY [[ADDI6]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.7.bb6:
- ; CHECK-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 200
- ; CHECK-NEXT: $x10 = COPY [[ADDI7]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.8.default:
- ; CHECK-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI $x0, 1000
- ; CHECK-NEXT: $x10 = COPY [[ADDI8]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- bb.1.entry:
- successors: %bb.8, %bb.9
- liveins: $x10
-
- %1:gprb(s64) = COPY $x10
- %2:gprb(s64) = G_ASSERT_SEXT %1, 32
- %7:gprb(s64) = G_CONSTANT i64 5
- %3:gprb(s64) = G_SEXT_INREG %2, 32
- %4:gprb(s64) = G_CONSTANT i64 1
- %5:gprb(s64) = G_SUB %3, %4
- %26:gprb(s64) = G_ICMP intpred(ugt), %5(s64), %7
- G_BRCOND %26(s64), %bb.8
-
- bb.9.entry:
- successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
-
- %10:gprb(p0) = G_JUMP_TABLE %jump-table.0
- G_BRJT %10(p0), %jump-table.0, %5(s64)
-
- bb.2.bb1:
- %22:gprb(s64) = G_CONSTANT i64 4
- $x10 = COPY %22(s64)
- PseudoRET implicit $x10
-
- bb.3.bb2:
- %20:gprb(s64) = G_CONSTANT i64 3
- $x10 = COPY %20(s64)
- PseudoRET implicit $x10
-
- bb.4.bb3:
- %18:gprb(s64) = G_CONSTANT i64 2
- $x10 = COPY %18(s64)
- PseudoRET implicit $x10
-
- bb.5.bb4:
- %16:gprb(s64) = G_CONSTANT i64 1
- $x10 = COPY %16(s64)
- PseudoRET implicit $x10
-
- bb.6.bb5:
- %14:gprb(s64) = G_CONSTANT i64 100
- $x10 = COPY %14(s64)
- PseudoRET implicit $x10
-
- bb.7.bb6:
- %12:gprb(s64) = G_CONSTANT i64 200
- $x10 = COPY %12(s64)
- PseudoRET implicit $x10
-
- bb.8.default:
- %24:gprb(s64) = G_CONSTANT i64 1000
- $x10 = COPY %24(s64)
- PseudoRET implicit $x10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
deleted file mode 100644
index 388c238b86eb6f4..000000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
+++ /dev/null
@@ -1,213 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select %s -o - \
-# RUN: -code-model=small | FileCheck %s --check-prefix=RV32-SMALL
-# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select %s -o - \
-# RUN: -code-model=medium | FileCheck %s --check-prefix=RV32-MEDIUM
-
---- |
- define i32 @jt_test(i32 signext %in) {
- entry:
- switch i32 %in, label %default [
- i32 1, label %bb1
- i32 2, label %bb2
- i32 3, label %bb3
- i32 4, label %bb4
- i32 5, label %bb5
- i32 6, label %bb6
- ]
-
- bb1: ; preds = %entry
- ret i32 4
-
- bb2: ; preds = %entry
- ret i32 3
-
- bb3: ; preds = %entry
- ret i32 2
-
- bb4: ; preds = %entry
- ret i32 1
-
- bb5: ; preds = %entry
- ret i32 100
-
- bb6: ; preds = %entry
- ret i32 200
-
- default: ; preds = %entry
- ret i32 1000
- }
-
-...
----
-name: jt_test
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-jumpTable:
- kind: block-address
- entries:
- - id: 0
- blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
-body: |
- ; RV32-SMALL-LABEL: name: jt_test
- ; RV32-SMALL: bb.0.entry:
- ; RV32-SMALL-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; RV32-SMALL-NEXT: liveins: $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV32-SMALL-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; RV32-SMALL-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 200
- ; RV32-SMALL-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 100
- ; RV32-SMALL-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 1
- ; RV32-SMALL-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
- ; RV32-SMALL-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 3
- ; RV32-SMALL-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 4
- ; RV32-SMALL-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 1000
- ; RV32-SMALL-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI [[COPY]], -1
- ; RV32-SMALL-NEXT: BLTU [[ADDI]], [[ADDI8]], %bb.8
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.1.entry:
- ; RV32-SMALL-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %jump-table.0
- ; RV32-SMALL-NEXT: [[ADDI9:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) %jump-table.0
- ; RV32-SMALL-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI8]], 2
- ; RV32-SMALL-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[ADDI9]], [[SLLI]]
- ; RV32-SMALL-NEXT: [[LW:%[0-9]+]]:gprjalr = LW [[ADD]], 0 :: (load (s32) from jump-table)
- ; RV32-SMALL-NEXT: PseudoBRIND [[LW]], 0
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.2.bb1:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI6]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.3.bb2:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI5]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.4.bb3:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI4]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.5.bb4:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI3]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.6.bb5:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI2]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.7.bb6:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI1]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ; RV32-SMALL-NEXT: {{ $}}
- ; RV32-SMALL-NEXT: bb.8.default:
- ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI7]]
- ; RV32-SMALL-NEXT: PseudoRET implicit $x10
- ;
- ; RV32-MEDIUM-LABEL: name: jt_test
- ; RV32-MEDIUM: bb.0.entry:
- ; RV32-MEDIUM-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; RV32-MEDIUM-NEXT: liveins: $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV32-MEDIUM-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; RV32-MEDIUM-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 200
- ; RV32-MEDIUM-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 100
- ; RV32-MEDIUM-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 1
- ; RV32-MEDIUM-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
- ; RV32-MEDIUM-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 3
- ; RV32-MEDIUM-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 4
- ; RV32-MEDIUM-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 1000
- ; RV32-MEDIUM-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI [[COPY]], -1
- ; RV32-MEDIUM-NEXT: BLTU [[ADDI]], [[ADDI8]], %bb.8
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.1.entry:
- ; RV32-MEDIUM-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA %jump-table.0
- ; RV32-MEDIUM-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI8]], 2
- ; RV32-MEDIUM-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLLA]], [[SLLI]]
- ; RV32-MEDIUM-NEXT: [[LW:%[0-9]+]]:gprjalr = LW [[ADD]], 0 :: (load (s32) from jump-table)
- ; RV32-MEDIUM-NEXT: PseudoBRIND [[LW]], 0
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.2.bb1:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI6]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.3.bb2:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI5]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.4.bb3:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI4]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.5.bb4:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI3]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.6.bb5:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI2]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.7.bb6:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI1]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- ; RV32-MEDIUM-NEXT: {{ $}}
- ; RV32-MEDIUM-NEXT: bb.8.default:
- ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI7]]
- ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
- bb.1.entry:
- successors: %bb.8, %bb.9
- liveins: $x10
-
- %0:gprb(s32) = COPY $x10
- %4:gprb(s32) = G_CONSTANT i32 5
- %8:gprb(s32) = G_CONSTANT i32 200
- %9:gprb(s32) = G_CONSTANT i32 100
- %10:gprb(s32) = G_CONSTANT i32 1
- %11:gprb(s32) = G_CONSTANT i32 2
- %12:gprb(s32) = G_CONSTANT i32 3
- %13:gprb(s32) = G_CONSTANT i32 4
- %14:gprb(s32) = G_CONSTANT i32 1000
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_SUB %0, %1
- %16:gprb(s32) = G_ICMP intpred(ugt), %2(s32), %4
- G_BRCOND %16(s32), %bb.8
-
- bb.9.entry:
- successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
-
- %7:gprb(p0) = G_JUMP_TABLE %jump-table.0
- G_BRJT %7(p0), %jump-table.0, %2(s32)
-
- bb.2.bb1:
- $x10 = COPY %13(s32)
- PseudoRET implicit $x10
-
- bb.3.bb2:
- $x10 = COPY %12(s32)
- PseudoRET implicit $x10
-
- bb.4.bb3:
- $x10 = COPY %11(s32)
- PseudoRET implicit $x10
-
- bb.5.bb4:
- $x10 = COPY %10(s32)
- PseudoRET implicit $x10
-
- bb.6.bb5:
- $x10 = COPY %9(s32)
- PseudoRET implicit $x10
-
- bb.7.bb6:
- $x10 = COPY %8(s32)
- PseudoRET implicit $x10
-
- bb.8.default:
- $x10 = COPY %14(s32)
- PseudoRET implicit $x10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
deleted file mode 100644
index 09a855105c26275..000000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
+++ /dev/null
@@ -1,161 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
-# RUN: -code-model=small | FileCheck %s
-
---- |
- define i32 @jt_test(i32 signext %in) {
- entry:
- %0 = sext i32 %in to i64
- switch i64 %0, label %default [
- i64 1, label %bb1
- i64 2, label %bb2
- i64 3, label %bb3
- i64 4, label %bb4
- i64 5, label %bb5
- i64 6, label %bb6
- ]
-
- bb1: ; preds = %entry
- ret i32 4
-
- bb2: ; preds = %entry
- ret i32 3
-
- bb3: ; preds = %entry
- ret i32 2
-
- bb4: ; preds = %entry
- ret i32 1
-
- bb5: ; preds = %entry
- ret i32 100
-
- bb6: ; preds = %entry
- ret i32 200
-
- default: ; preds = %entry
- ret i32 1000
- }
-
-...
----
-name: jt_test
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-jumpTable:
- kind: custom32
- entries:
- - id: 0
- blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
-body: |
- ; CHECK-LABEL: name: jt_test
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
- ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[ADDIW]], -1
- ; CHECK-NEXT: BLTU [[ADDI]], [[ADDI1]], %bb.8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.entry:
- ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %jump-table.0
- ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) %jump-table.0
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI1]], 2
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[ADDI2]], [[SLLI]]
- ; CHECK-NEXT: [[LW:%[0-9]+]]:gprjalr = LW [[ADD]], 0 :: (load (s32) from jump-table)
- ; CHECK-NEXT: PseudoBRIND [[LW]], 0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 4
- ; CHECK-NEXT: $x10 = COPY [[ADDI3]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.bb2:
- ; CHECK-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: $x10 = COPY [[ADDI4]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.bb3:
- ; CHECK-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 2
- ; CHECK-NEXT: $x10 = COPY [[ADDI5]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.5.bb4:
- ; CHECK-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 1
- ; CHECK-NEXT: $x10 = COPY [[ADDI6]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.6.bb5:
- ; CHECK-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 100
- ; CHECK-NEXT: $x10 = COPY [[ADDI7]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.7.bb6:
- ; CHECK-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI $x0, 200
- ; CHECK-NEXT: $x10 = COPY [[ADDI8]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.8.default:
- ; CHECK-NEXT: [[ADDI9:%[0-9]+]]:gpr = ADDI $x0, 1000
- ; CHECK-NEXT: $x10 = COPY [[ADDI9]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- bb.1.entry:
- successors: %bb.8, %bb.9
- liveins: $x10
-
- %1:gprb(s64) = COPY $x10
- %2:gprb(s64) = G_ASSERT_SEXT %1, 32
- %7:gprb(s64) = G_CONSTANT i64 5
- %3:gprb(s64) = G_SEXT_INREG %2, 32
- %4:gprb(s64) = G_CONSTANT i64 1
- %5:gprb(s64) = G_SUB %3, %4
- %26:gprb(s64) = G_ICMP intpred(ugt), %5(s64), %7
- G_BRCOND %26(s64), %bb.8
-
- bb.9.entry:
- successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
-
- %10:gprb(p0) = G_JUMP_TABLE %jump-table.0
- G_BRJT %10(p0), %jump-table.0, %5(s64)
-
- bb.2.bb1:
- %22:gprb(s64) = G_CONSTANT i64 4
- $x10 = COPY %22(s64)
- PseudoRET implicit $x10
-
- bb.3.bb2:
- %20:gprb(s64) = G_CONSTANT i64 3
- $x10 = COPY %20(s64)
- PseudoRET implicit $x10
-
- bb.4.bb3:
- %18:gprb(s64) = G_CONSTANT i64 2
- $x10 = COPY %18(s64)
- PseudoRET implicit $x10
-
- bb.5.bb4:
- %16:gprb(s64) = G_CONSTANT i64 1
- $x10 = COPY %16(s64)
- PseudoRET implicit $x10
-
- bb.6.bb5:
- %14:gprb(s64) = G_CONSTANT i64 100
- $x10 = COPY %14(s64)
- PseudoRET implicit $x10
-
- bb.7.bb6:
- %12:gprb(s64) = G_CONSTANT i64 200
- $x10 = COPY %12(s64)
- PseudoRET implicit $x10
-
- bb.8.default:
- %24:gprb(s64) = G_CONSTANT i64 1000
- $x10 = COPY %24(s64)
- PseudoRET implicit $x10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/jumptable.ll b/llvm/test/CodeGen/RISCV/GlobalISel/jumptable.ll
index 601290812bb2e66..c9d8ec2c8781b7c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/jumptable.ll
@@ -94,7 +94,7 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
; RV32I-PIC-NEXT: slli a0, a0, 2
; RV32I-PIC-NEXT: add a0, a2, a0
; RV32I-PIC-NEXT: lw a0, 0(a0)
-; RV32I-PIC-NEXT: add a0, a0, a2
+; RV32I-PIC-NEXT: add a0, a2, a0
; RV32I-PIC-NEXT: jr a0
; RV32I-PIC-NEXT: .LBB0_2: # %bb1
; RV32I-PIC-NEXT: li a0, 4
@@ -202,7 +202,7 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
; RV64I-PIC-NEXT: slli a0, a0, 2
; RV64I-PIC-NEXT: add a0, a2, a0
; RV64I-PIC-NEXT: lw a0, 0(a0)
-; RV64I-PIC-NEXT: add a0, a0, a2
+; RV64I-PIC-NEXT: add a0, a2, a0
; RV64I-PIC-NEXT: jr a0
; RV64I-PIC-NEXT: .LBB0_2: # %bb1
; RV64I-PIC-NEXT: li a0, 4
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir
new file mode 100644
index 000000000000000..530bd98a625a57e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir
@@ -0,0 +1,163 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: -code-model=medium | FileCheck %s
+
+--- |
+ define i32 @jt_test(i32 signext %in) {
+ entry:
+ %0 = sext i32 %in to i64
+ switch i64 %0, label %default [
+ i64 1, label %bb1
+ i64 2, label %bb2
+ i64 3, label %bb3
+ i64 4, label %bb4
+ i64 5, label %bb5
+ i64 6, label %bb6
+ ]
+
+ bb1:
+ ret i32 4
+
+ bb2:
+ ret i32 3
+
+ bb3:
+ ret i32 2
+
+ bb4:
+ ret i32 1
+
+ bb5:
+ ret i32 100
+
+ bb6:
+ ret i32 200
+
+ default:
+ ret i32 1000
+ }
+
+...
+---
+name: jt_test
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
+body: |
+ ; CHECK-LABEL: name: jt_test
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_SEXT]], 32
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s64), %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from jump-table)
+ ; CHECK-NEXT: G_BRINDIRECT [[LOAD]](p0)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb1:
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: $x10 = COPY [[C3]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb2:
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: $x10 = COPY [[C4]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb3:
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: $x10 = COPY [[C5]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb4:
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: $x10 = COPY [[C6]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb5:
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
+ ; CHECK-NEXT: $x10 = COPY [[C7]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb6:
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 200
+ ; CHECK-NEXT: $x10 = COPY [[C8]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.default:
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000
+ ; CHECK-NEXT: $x10 = COPY [[C9]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ bb.1.entry:
+ successors: %bb.8, %bb.9
+ liveins: $x10
+
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = G_ASSERT_SEXT %1, 32
+ %0:_(s32) = G_TRUNC %2(s64)
+ %7:_(s64) = G_CONSTANT i64 5
+ %3:_(s64) = G_SEXT %0(s32)
+ %4:_(s64) = G_CONSTANT i64 1
+ %5:_(s64) = G_SUB %3, %4
+ %9:_(s1) = G_ICMP intpred(ugt), %5(s64), %7
+ G_BRCOND %9(s1), %bb.8
+
+ bb.9.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+
+ %10:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %10(p0), %jump-table.0, %5(s64)
+
+ bb.2.bb1:
+ %22:_(s64) = G_CONSTANT i64 4
+ $x10 = COPY %22(s64)
+ PseudoRET implicit $x10
+
+ bb.3.bb2:
+ %20:_(s64) = G_CONSTANT i64 3
+ $x10 = COPY %20(s64)
+ PseudoRET implicit $x10
+
+ bb.4.bb3:
+ %18:_(s64) = G_CONSTANT i64 2
+ $x10 = COPY %18(s64)
+ PseudoRET implicit $x10
+
+ bb.5.bb4:
+ %16:_(s64) = G_CONSTANT i64 1
+ $x10 = COPY %16(s64)
+ PseudoRET implicit $x10
+
+ bb.6.bb5:
+ %14:_(s64) = G_CONSTANT i64 100
+ $x10 = COPY %14(s64)
+ PseudoRET implicit $x10
+
+ bb.7.bb6:
+ %12:_(s64) = G_CONSTANT i64 200
+ $x10 = COPY %12(s64)
+ PseudoRET implicit $x10
+
+ bb.8.default:
+ %24:_(s64) = G_CONSTANT i64 1000
+ $x10 = COPY %24(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv32.mir
similarity index 56%
rename from llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv32.mir
index 27fe465ccf696bf..41b90724754dc15 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: -relocation-model=pic | FileCheck %s
--- |
@@ -39,8 +39,6 @@
...
---
name: jt_test
-legalized: true
-regBankSelected: true
tracksRegLiveness: true
jumpTable:
kind: label-difference32
@@ -53,77 +51,81 @@ body: |
; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 200
- ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 100
- ; CHECK-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 1
- ; CHECK-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
- ; CHECK-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 4
- ; CHECK-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 1000
- ; CHECK-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI [[COPY]], -1
- ; CHECK-NEXT: BLTU [[ADDI]], [[ADDI8]], %bb.8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 200
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C8]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA %jump-table.0
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI8]], 2
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLLA]], [[SLLI]]
- ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[ADD]], 0 :: (load (s32) from jump-table)
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gprjalr = ADD [[LW]], [[PseudoLLA]]
- ; CHECK-NEXT: PseudoBRIND [[ADD1]], 0
+ ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C9]](s32)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[COPY1]](s32)
+ ; CHECK-NEXT: G_BRINDIRECT [[PTR_ADD1]](p0)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: $x10 = COPY [[ADDI6]]
+ ; CHECK-NEXT: $x10 = COPY [[C6]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb2:
- ; CHECK-NEXT: $x10 = COPY [[ADDI5]]
+ ; CHECK-NEXT: $x10 = COPY [[C5]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.bb3:
- ; CHECK-NEXT: $x10 = COPY [[ADDI4]]
+ ; CHECK-NEXT: $x10 = COPY [[C4]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.bb4:
- ; CHECK-NEXT: $x10 = COPY [[ADDI3]]
+ ; CHECK-NEXT: $x10 = COPY [[C3]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.bb5:
- ; CHECK-NEXT: $x10 = COPY [[ADDI2]]
+ ; CHECK-NEXT: $x10 = COPY [[C2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.bb6:
- ; CHECK-NEXT: $x10 = COPY [[ADDI1]]
+ ; CHECK-NEXT: $x10 = COPY [[C1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.default:
- ; CHECK-NEXT: $x10 = COPY [[ADDI7]]
+ ; CHECK-NEXT: $x10 = COPY [[C7]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
bb.1.entry:
successors: %bb.8, %bb.9
liveins: $x10
- %0:gprb(s32) = COPY $x10
- %4:gprb(s32) = G_CONSTANT i32 5
- %8:gprb(s32) = G_CONSTANT i32 200
- %9:gprb(s32) = G_CONSTANT i32 100
- %10:gprb(s32) = G_CONSTANT i32 1
- %11:gprb(s32) = G_CONSTANT i32 2
- %12:gprb(s32) = G_CONSTANT i32 3
- %13:gprb(s32) = G_CONSTANT i32 4
- %14:gprb(s32) = G_CONSTANT i32 1000
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_SUB %0, %1
- %16:gprb(s32) = G_ICMP intpred(ugt), %2(s32), %4
- G_BRCOND %16(s32), %bb.8
+ %0:_(s32) = COPY $x10
+ %4:_(s32) = G_CONSTANT i32 5
+ %8:_(s32) = G_CONSTANT i32 200
+ %9:_(s32) = G_CONSTANT i32 100
+ %10:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_CONSTANT i32 2
+ %12:_(s32) = G_CONSTANT i32 3
+ %13:_(s32) = G_CONSTANT i32 4
+ %14:_(s32) = G_CONSTANT i32 1000
+ %1:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_SUB %0, %1
+ %6:_(s1) = G_ICMP intpred(ugt), %2(s32), %4
+ G_BRCOND %6(s1), %bb.8
bb.9.entry:
successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
- %7:gprb(p0) = G_JUMP_TABLE %jump-table.0
+ %7:_(p0) = G_JUMP_TABLE %jump-table.0
G_BRJT %7(p0), %jump-table.0, %2(s32)
bb.2.bb1:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir
new file mode 100644
index 000000000000000..76403e8cc6f4c3b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir
@@ -0,0 +1,165 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: -relocation-model=pic | FileCheck %s
+
+--- |
+ define i32 @jt_test(i32 signext %in) {
+ entry:
+ %0 = sext i32 %in to i64
+ switch i64 %0, label %default [
+ i64 1, label %bb1
+ i64 2, label %bb2
+ i64 3, label %bb3
+ i64 4, label %bb4
+ i64 5, label %bb5
+ i64 6, label %bb6
+ ]
+
+ bb1:
+ ret i32 4
+
+ bb2:
+ ret i32 3
+
+ bb3:
+ ret i32 2
+
+ bb4:
+ ret i32 1
+
+ bb5:
+ ret i32 100
+
+ bb6:
+ ret i32 200
+
+ default:
+ ret i32 1000
+ }
+
+...
+---
+name: jt_test
+tracksRegLiveness: true
+jumpTable:
+ kind: label-difference32
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
+body: |
+ ; CHECK-LABEL: name: jt_test
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_SEXT]], 32
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s64), %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SEXT]](s64)
+ ; CHECK-NEXT: G_BRINDIRECT [[PTR_ADD1]](p0)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb1:
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: $x10 = COPY [[C3]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb2:
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: $x10 = COPY [[C4]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb3:
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: $x10 = COPY [[C5]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb4:
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: $x10 = COPY [[C6]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb5:
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
+ ; CHECK-NEXT: $x10 = COPY [[C7]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb6:
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 200
+ ; CHECK-NEXT: $x10 = COPY [[C8]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.default:
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000
+ ; CHECK-NEXT: $x10 = COPY [[C9]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ bb.1.entry:
+ successors: %bb.8, %bb.9
+ liveins: $x10
+
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = G_ASSERT_SEXT %1, 32
+ %0:_(s32) = G_TRUNC %2(s64)
+ %7:_(s64) = G_CONSTANT i64 5
+ %3:_(s64) = G_SEXT %0(s32)
+ %4:_(s64) = G_CONSTANT i64 1
+ %5:_(s64) = G_SUB %3, %4
+ %9:_(s1) = G_ICMP intpred(ugt), %5(s64), %7
+ G_BRCOND %9(s1), %bb.8
+
+ bb.9.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+
+ %10:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %10(p0), %jump-table.0, %5(s64)
+
+ bb.2.bb1:
+ %22:_(s64) = G_CONSTANT i64 4
+ $x10 = COPY %22(s64)
+ PseudoRET implicit $x10
+
+ bb.3.bb2:
+ %20:_(s64) = G_CONSTANT i64 3
+ $x10 = COPY %20(s64)
+ PseudoRET implicit $x10
+
+ bb.4.bb3:
+ %18:_(s64) = G_CONSTANT i64 2
+ $x10 = COPY %18(s64)
+ PseudoRET implicit $x10
+
+ bb.5.bb4:
+ %16:_(s64) = G_CONSTANT i64 1
+ $x10 = COPY %16(s64)
+ PseudoRET implicit $x10
+
+ bb.6.bb5:
+ %14:_(s64) = G_CONSTANT i64 100
+ $x10 = COPY %14(s64)
+ PseudoRET implicit $x10
+
+ bb.7.bb6:
+ %12:_(s64) = G_CONSTANT i64 200
+ $x10 = COPY %12(s64)
+ PseudoRET implicit $x10
+
+ bb.8.default:
+ %24:_(s64) = G_CONSTANT i64 1000
+ $x10 = COPY %24(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir
index a7fd7da77261f84..97e2badb3ed0ed6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
-# RUN: | FileCheck %s
+# RUN: -code-model=small | FileCheck %s
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: -code-model=medium | FileCheck %s
--- |
define i32 @jt_test(i32 signext %in) {
@@ -69,7 +71,11 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
- ; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s32)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C9]](s32)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table)
+ ; CHECK-NEXT: G_BRINDIRECT [[LOAD]](p0)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb1:
; CHECK-NEXT: $x10 = COPY [[C6]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-small-rv64.mir
similarity index 81%
rename from llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv64.mir
rename to llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-small-rv64.mir
index 9910e98a3e8200f..282002ea65e293e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-small-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
-# RUN: | FileCheck %s
+# RUN: -code-model=small | FileCheck %s
--- |
define i32 @jt_test(i32 signext %in) {
@@ -65,41 +65,46 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
- ; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s64)
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SEXTLOAD]](s64)
+ ; CHECK-NEXT: G_BRINDIRECT [[INTTOPTR]](p0)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: $x10 = COPY [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: $x10 = COPY [[C3]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb2:
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: $x10 = COPY [[C3]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: $x10 = COPY [[C4]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.bb3:
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: $x10 = COPY [[C4]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: $x10 = COPY [[C5]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.bb4:
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: $x10 = COPY [[C5]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: $x10 = COPY [[C6]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.bb5:
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
- ; CHECK-NEXT: $x10 = COPY [[C6]](s64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
+ ; CHECK-NEXT: $x10 = COPY [[C7]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.bb6:
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 200
- ; CHECK-NEXT: $x10 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 200
+ ; CHECK-NEXT: $x10 = COPY [[C8]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.default:
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000
- ; CHECK-NEXT: $x10 = COPY [[C8]](s64)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000
+ ; CHECK-NEXT: $x10 = COPY [[C9]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
bb.1.entry:
successors: %bb.8, %bb.9
>From 2f83efbe3db0cbd9577f30e2902fd986a8551646 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 28 Nov 2023 20:59:54 -0800
Subject: [PATCH 2/3] fixup! reuse IndexReg.
---
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 3d82a4cffbe629e..d0e6749c8217bbe 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -330,14 +330,13 @@ bool RISCVLegalizerInfo::legalizeBRJT(MachineInstr &MI,
Register IndexReg = MI.getOperand(2).getReg();
LLT IndexTy = MRI.getType(IndexReg);
- MachineInstrBuilder Index;
if (isPowerOf2_32(EntrySize)) {
auto ShiftAmt = MIRBuilder.buildConstant(IndexTy, Log2_32(EntrySize));
- Index = MIRBuilder.buildShl(IndexTy, IndexReg, ShiftAmt);
+ IndexReg = MIRBuilder.buildShl(IndexTy, IndexReg, ShiftAmt).getReg(0);
} else
return false;
- auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, Index);
+ auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, IndexReg);
MachineMemOperand *MMO = MF.getMachineMemOperand(
MachinePointerInfo::getJumpTable(MF), MachineMemOperand::MOLoad,
>From fd463cf006c95c8925933666333ecc836d7ecdd1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 28 Nov 2023 21:02:18 -0800
Subject: [PATCH 3/3] fixup! return false for unknown entry kind
---
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index d0e6749c8217bbe..a9c5fc4e9debcc2 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -345,7 +345,7 @@ bool RISCVLegalizerInfo::legalizeBRJT(MachineInstr &MI,
Register TargetReg;
switch (MJTI->getEntryKind()) {
default:
- llvm_unreachable("Unexpected jumptable entry kind");
+ return false;
case MachineJumpTableInfo::EK_LabelDifference32: {
// For PIC, the sequence is:
// BRIND(load(Jumptable + index) + RelocBase)
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