[llvm] AMDGPU/GlobalISel: Uniformity info based regbankselect (PR #73684)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 10:36:40 PST 2023
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/73684
RFC for approach in rewriting reg-bank-selection using machine uniformity info analysis.
Implemented only for one opcode in this patch.
Current proposal in to pre-select register banks on dst registers using MUI before regbankselection starts.
Then using pre-assigned dst reg banks, instead of looking into register banks for inputs, select register banks for instructions so that available machine instructions could be instruction-selected
>From f7c8f7fc1d440cf64d776f72f6ac89930e1e2a6f Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Tue, 28 Nov 2023 19:07:58 +0100
Subject: [PATCH 1/2] AMDGPU/GlobalISel: refactor build readfirstlane helpers
Refactor helpers that build readfirstlane for input registers.
Required by upcoming patches thet need to build readfirstlane
for output registers.
---
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 89 +++++++++++--------
.../Target/AMDGPU/AMDGPURegisterBankInfo.h | 22 ++++-
2 files changed, 73 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 62996a3b3fb79fb..6700e2405310fb7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -695,58 +695,75 @@ static LLT getHalfSizedType(LLT Ty) {
// Build one or more V_READFIRSTLANE_B32 instructions to move the given vector
// source value into a scalar register.
-Register AMDGPURegisterBankInfo::buildReadFirstLane(MachineIRBuilder &B,
- MachineRegisterInfo &MRI,
- Register Src) const {
+Register AMDGPURegisterBankInfo::buildReadFirstLaneSrc(MachineIRBuilder &B,
+ Register Src) const {
+ MachineRegisterInfo &MRI = *B.getMRI();
LLT Ty = MRI.getType(Src);
const RegisterBank *Bank = getRegBank(Src, MRI, *TRI);
- if (Bank == &AMDGPU::SGPRRegBank)
- return Src;
-
- unsigned Bits = Ty.getSizeInBits();
- assert(Bits % 32 == 0);
-
if (Bank != &AMDGPU::VGPRRegBank) {
// We need to copy from AGPR to VGPR
Src = B.buildCopy(Ty, Src).getReg(0);
MRI.setRegBank(Src, AMDGPU::VGPRRegBank);
}
+ Register Dst = MRI.createGenericVirtualRegister(Ty);
+ MRI.setRegBank(Dst, AMDGPU::SGPRRegBank);
+ buildReadFirstLaneForType(B, Dst, Src);
+ return Dst;
+}
+
+void AMDGPURegisterBankInfo::buildReadFirstLaneB32(MachineIRBuilder &B,
+ Register SgprDst,
+ Register VgprSrc) const {
+ MachineRegisterInfo &MRI = *B.getMRI();
+ B.buildInstr(AMDGPU::V_READFIRSTLANE_B32, {SgprDst}, {VgprSrc});
+ MRI.setRegClass(VgprSrc, &AMDGPU::VGPR_32RegClass);
+ MRI.setRegClass(SgprDst, &AMDGPU::SReg_32RegClass);
+}
+
+void AMDGPURegisterBankInfo::buildReadFirstLaneSequenceOfB32(
+ MachineIRBuilder &B, Register SgprDst, Register VgprSrc,
+ unsigned NumElts) const {
+ MachineRegisterInfo &MRI = *B.getMRI();
LLT S32 = LLT::scalar(32);
- unsigned NumParts = Bits / 32;
- SmallVector<Register, 8> SrcParts;
- SmallVector<Register, 8> DstParts;
+ SmallVector<Register, 8> VgprSrcParts;
+ SmallVector<Register, 8> SgprDstParts;
- if (Bits == 32) {
- SrcParts.push_back(Src);
- } else {
- auto Unmerge = B.buildUnmerge(S32, Src);
- for (unsigned i = 0; i < NumParts; ++i)
- SrcParts.push_back(Unmerge.getReg(i));
+ for (unsigned i = 0; i < NumElts; ++i) {
+ VgprSrcParts.push_back(MRI.createGenericVirtualRegister(S32));
+ SgprDstParts.push_back(MRI.createGenericVirtualRegister(S32));
}
- for (unsigned i = 0; i < NumParts; ++i) {
- Register SrcPart = SrcParts[i];
- Register DstPart = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
- MRI.setType(DstPart, NumParts == 1 ? Ty : S32);
+ B.buildUnmerge(VgprSrcParts, VgprSrc);
+ for (unsigned i = 0; i < NumElts; ++i) {
+ buildReadFirstLaneB32(B, SgprDstParts[i], VgprSrcParts[i]);
+ }
+ B.buildMergeLikeInstr(SgprDst, SgprDstParts);
+}
- const TargetRegisterClass *Constrained =
- constrainGenericRegister(SrcPart, AMDGPU::VGPR_32RegClass, MRI);
- (void)Constrained;
- assert(Constrained && "Failed to constrain readfirstlane src reg");
+void AMDGPURegisterBankInfo::buildReadFirstLaneForType(MachineIRBuilder &B,
+ Register SgprDst,
+ Register VgprSrc) const {
+ MachineRegisterInfo &MRI = *B.getMRI();
+ LLT S32 = LLT::scalar(32);
+ LLT S64 = LLT::scalar(64);
+ LLT Ty = MRI.getType(SgprDst);
- B.buildInstr(AMDGPU::V_READFIRSTLANE_B32, {DstPart}, {SrcPart});
+ if (Ty == S32 || Ty == LLT::pointer(3, 32)) {
+ return buildReadFirstLaneB32(B, SgprDst, VgprSrc);
+ }
- DstParts.push_back(DstPart);
+ if (Ty == S64 || Ty == LLT::pointer(0, 64) || Ty == LLT::pointer(1, 64)) {
+ return buildReadFirstLaneSequenceOfB32(B, SgprDst, VgprSrc, 2);
}
- if (Bits == 32)
- return DstParts[0];
+ if (Ty.isVector() && Ty.getElementType() == S32) {
+ return buildReadFirstLaneSequenceOfB32(B, SgprDst, VgprSrc,
+ Ty.getNumElements());
+ }
- Register Dst = B.buildMergeLikeInstr(Ty, DstParts).getReg(0);
- MRI.setRegBank(Dst, AMDGPU::SGPRRegBank);
- return Dst;
+ llvm_unreachable("Type not supported");
}
/// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs. If
@@ -883,7 +900,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
B.setMBB(*LoopBB);
}
- Register CurrentLaneReg = buildReadFirstLane(B, MRI, OpReg);
+ Register CurrentLaneReg = buildReadFirstLaneSrc(B, OpReg);
// Build the comparison(s).
unsigned OpSize = OpTy.getSizeInBits();
@@ -1015,7 +1032,7 @@ void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(
if (Bank == &AMDGPU::SGPRRegBank)
return;
- Reg = buildReadFirstLane(B, MRI, Reg);
+ Reg = buildReadFirstLaneSrc(B, Reg);
MI.getOperand(OpIdx).setReg(Reg);
}
@@ -1591,7 +1608,7 @@ bool AMDGPURegisterBankInfo::applyMappingMAD_64_32(
MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank);
if (!DstOnValu) {
- DstHi = buildReadFirstLane(B, MRI, DstHi);
+ DstHi = buildReadFirstLaneSrc(B, DstHi);
} else {
MulHiInVgpr = true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
index b5d16e70ab23a20..1236019e909e9e7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
@@ -57,8 +57,17 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
iterator_range<MachineBasicBlock::iterator> Range,
SmallSet<Register, 4> &SGPROperandRegs) const;
- Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
- Register Src) const;
+ Register buildReadFirstLaneSrc(MachineIRBuilder &B, Register Src) const;
+
+ void buildReadFirstLaneForType(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc) const;
+
+ void buildReadFirstLaneB32(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc) const;
+
+ void buildReadFirstLaneSequenceOfB32(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc,
+ unsigned NumElts) const;
bool executeInWaterfallLoop(MachineIRBuilder &B, MachineInstr &MI,
ArrayRef<unsigned> OpIndices) const;
@@ -113,6 +122,12 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const;
+ // Return a value mapping for an operand that is same as already assigned
+ // reg bank or corresponds to assigned register class + LLT
+ const ValueMapping *
+ getPreAssignedOpMapping(Register Reg, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const;
+
// Return a value mapping for an operand that is required to be a AGPR.
const ValueMapping *getAGPROpMapping(Register Reg,
const MachineRegisterInfo &MRI,
@@ -152,6 +167,9 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
+ const InstructionMapping &
+ getDefaultMappingVOPWithPreassignedDef(const MachineInstr &MI) const;
+
const InstructionMapping &getDefaultMappingAllVGPR(
const MachineInstr &MI) const;
>From 298808609322d0c289433eeaa346758d0c20d442 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Tue, 28 Nov 2023 19:26:52 +0100
Subject: [PATCH 2/2] AMDGPU/GlobalISel: uniformity analysis based register
bank selection
Current algorithm only considers register banks for inputs but does
take control flow into account.
This is wrong in cases where inputs are uniform (in sgpr) but because
of divergent control flow instruction is divergent and should use vgpr
instead of sgpr register banks. Most notable example are phis.
Also in cases where only available machine instruction uses vgpr
registers uniform instructions end up using vgpr register banks.
Start with simple implementation for G_FADD.
Pre-select register bank for destination register using machine
uniformity analysis info. Then select register banks that would allow
selection of available machine instructions.
For G_FADD vgpr machine instruction is available on all targets but
sgpr version is not. When there is no sgpr version assign vgpr register
banks and move vgpr destination to sgpr using readfirstlane.
---
.../lib/Target/AMDGPU/AMDGPURegBankSelect.cpp | 22 +-
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 113 +++-
.../Target/AMDGPU/AMDGPURegisterBankInfo.h | 6 +
.../GlobalISel/combine-fma-add-ext-mul.ll | 74 +-
.../CodeGen/AMDGPU/GlobalISel/floor.f64.ll | 16 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 17 +-
.../GlobalISel/llvm.amdgcn.interp.inreg.ll | 3 +
.../AMDGPU/GlobalISel/regbankselect-fadd.mir | 3 +-
.../test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll | 638 +++++++++---------
.../test/CodeGen/AMDGPU/GlobalISel/udivrem.ll | 266 ++++----
llvm/test/CodeGen/AMDGPU/llvm.exp.ll | 399 ++++++-----
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll | 166 +++--
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 440 +++++++-----
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 440 +++++++-----
14 files changed, 1575 insertions(+), 1028 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
index 2ea03ddb1fccd6c..ca9c70e7ed4a017 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
@@ -15,7 +15,10 @@
#include "AMDGPURegBankSelect.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
+#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/InitializePasses.h"
#define DEBUG_TYPE "regbankselect"
@@ -68,7 +71,24 @@ bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
MachineUniformityInfo Uniformity =
computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase(),
!ST.isSingleLaneExecution(F));
- (void)Uniformity; // TODO: Use this
+
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ switch (MI.getOpcode()) {
+ case AMDGPU::G_FADD: {
+ Register Dst = MI.getOperand(0).getReg();
+ if (Uniformity.isUniform(Dst)) {
+ MRI->setRegBank(Dst, RBI->getRegBank(AMDGPU::SGPRRegBankID));
+ } else {
+ MRI->setRegBank(Dst, RBI->getRegBank(AMDGPU::VGPRRegBankID));
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ }
assignRegisterBanks(MF);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 6700e2405310fb7..b8d6a3bd3c0e6fc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -713,6 +713,26 @@ Register AMDGPURegisterBankInfo::buildReadFirstLaneSrc(MachineIRBuilder &B,
return Dst;
}
+// Create new vgpr destination register for MI then move it to current
+// MI's sgpr destination using one or more V_READFIRSTLANE_B32 instructions.
+void AMDGPURegisterBankInfo::buildReadFirstLaneDst(MachineIRBuilder &B,
+ MachineInstr &MI) const {
+ MachineRegisterInfo &MRI = *B.getMRI();
+ Register Dst = MI.getOperand(0).getReg();
+ const RegisterBank *DstBank = getRegBank(Dst, MRI, *TRI);
+ if (DstBank != &AMDGPU::SGPRRegBank)
+ return;
+
+ Register VgprDst = MRI.createGenericVirtualRegister(MRI.getType(Dst));
+ MRI.setRegBank(VgprDst, AMDGPU::VGPRRegBank);
+
+ MI.getOperand(0).setReg(VgprDst);
+ MachineBasicBlock *MBB = MI.getParent();
+ B.setInsertPt(*MBB, std::next(MI.getIterator()));
+ // readFirstLane VgprDst into Dst after MI.
+ return buildReadFirstLaneForType(B, Dst, VgprDst);
+}
+
void AMDGPURegisterBankInfo::buildReadFirstLaneB32(MachineIRBuilder &B,
Register SgprDst,
Register VgprSrc) const {
@@ -746,10 +766,23 @@ void AMDGPURegisterBankInfo::buildReadFirstLaneForType(MachineIRBuilder &B,
Register SgprDst,
Register VgprSrc) const {
MachineRegisterInfo &MRI = *B.getMRI();
+ LLT S16 = LLT::scalar(16);
LLT S32 = LLT::scalar(32);
LLT S64 = LLT::scalar(64);
LLT Ty = MRI.getType(SgprDst);
+ if (Ty == S16) {
+ Register VgprSrc32 = MRI.createGenericVirtualRegister(S32);
+ MRI.setRegBank(VgprSrc32, AMDGPU::VGPRRegBank);
+ Register SgprDst32 = MRI.createGenericVirtualRegister(S32);
+ MRI.setRegBank(SgprDst32, AMDGPU::SGPRRegBank);
+
+ B.buildAnyExt(VgprSrc32, VgprSrc);
+ buildReadFirstLaneB32(B, SgprDst32, VgprSrc32);
+ B.buildTrunc(SgprDst, SgprDst32);
+ return;
+ }
+
if (Ty == S32 || Ty == LLT::pointer(3, 32)) {
return buildReadFirstLaneB32(B, SgprDst, VgprSrc);
}
@@ -1036,6 +1069,19 @@ void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(
MI.getOperand(OpIdx).setReg(Reg);
}
+// MI has uniform inputs and output but only available machine instruction has
+// vgpr dest. Make it uniform by moving dst to sgpr using readfirstlane.
+void AMDGPURegisterBankInfo::constrainVgprDstOpWithReadfirstlane(
+ MachineIRBuilder &B, MachineInstr &MI,
+ const OperandsMapper &OpdMapper) const {
+ const RegisterBank *DstBank =
+ OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
+ if (DstBank != &AMDGPU::VGPRRegBank)
+ buildReadFirstLaneDst(B, MI);
+
+ return;
+}
+
/// Split \p Ty into 2 pieces. The first will have \p FirstSize bits, and the
/// rest will be in the remainder.
static std::pair<LLT, LLT> splitUnequalType(LLT Ty, unsigned FirstSize) {
@@ -2117,6 +2163,17 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
B.setInstrAndDebugLoc(MI);
unsigned Opc = MI.getOpcode();
MachineRegisterInfo &MRI = OpdMapper.getMRI();
+
+ switch (Opc) {
+ case AMDGPU::G_FADD:
+ applyDefaultMapping(OpdMapper);
+ if (!Subtarget.hasSALUFloatInsts())
+ constrainVgprDstOpWithReadfirstlane(B, MI, OpdMapper);
+ return;
+ default:
+ break;
+ }
+
switch (Opc) {
case AMDGPU::G_CONSTANT:
case AMDGPU::G_IMPLICIT_DEF: {
@@ -3372,6 +3429,28 @@ AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
MI.getNumOperands());
}
+const RegisterBankInfo::InstructionMapping &
+AMDGPURegisterBankInfo::getDefaultMappingVOPWithPreassignedDef(
+ const MachineInstr &MI) const {
+ SmallVector<const ValueMapping *, 8> OpdsMapping(MI.getNumOperands());
+ const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
+ // Dst reg bank should have been set already by uniformity info
+ OpdsMapping[0] =
+ getPreAssignedOpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
+
+ for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i) {
+ const MachineOperand &Op = MI.getOperand(i);
+ if (!Op.isReg())
+ continue;
+
+ unsigned Size = getSizeInBits(Op.getReg(), MRI, *TRI);
+ unsigned BankID = Size == 1 ? AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID;
+ OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
+ }
+ return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
+ MI.getNumOperands());
+}
+
const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
@@ -3524,6 +3603,22 @@ AMDGPURegisterBankInfo::getVGPROpMapping(Register Reg,
return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
}
+const RegisterBankInfo::ValueMapping *
+AMDGPURegisterBankInfo::getPreAssignedOpMapping(
+ Register Reg, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const {
+ const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
+ assert(Bank);
+ unsigned BankId = Bank->getID();
+ unsigned Size = getSizeInBits(Reg, MRI, TRI);
+ if (Size != 1)
+ assert(BankId == AMDGPU::SGPRRegBankID || BankId == AMDGPU::VGPRRegBankID);
+ else
+ assert(BankId == AMDGPU::SGPRRegBankID || BankId == AMDGPU::VCCRegBankID);
+
+ return AMDGPU::getValueMapping(BankId, Size);
+}
+
const RegisterBankInfo::ValueMapping *
AMDGPURegisterBankInfo::getAGPROpMapping(Register Reg,
const MachineRegisterInfo &MRI,
@@ -3640,6 +3735,23 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
+ // Switch for uniformity info based regbank selection.
+ // Does not inspect register bank on incoming operands.
+ switch (MI.getOpcode()) {
+ case AMDGPU::G_FADD: {
+ if (!Subtarget.hasSALUFloatInsts())
+ return getDefaultMappingVOPWithPreassignedDef(MI);
+
+ unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ if (Subtarget.hasSALUFloatInsts() && (Size == 32 || Size == 16) &&
+ isSALUMapping(MI))
+ return getDefaultMappingSOP(MI);
+ return getDefaultMappingVOP(MI);
+ }
+ default:
+ break;
+ }
+
switch (MI.getOpcode()) {
default:
return getInvalidInstructionMapping();
@@ -3735,7 +3847,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (isSALUMapping(MI))
return getDefaultMappingSOP(MI);
return getDefaultMappingVOP(MI);
- case AMDGPU::G_FADD:
case AMDGPU::G_FSUB:
case AMDGPU::G_FMUL:
case AMDGPU::G_FMA:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
index 1236019e909e9e7..c4a130eb147fea7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
@@ -59,6 +59,8 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
Register buildReadFirstLaneSrc(MachineIRBuilder &B, Register Src) const;
+ void buildReadFirstLaneDst(MachineIRBuilder &B, MachineInstr &MI) const;
+
void buildReadFirstLaneForType(MachineIRBuilder &B, Register SgprDst,
Register VgprSrc) const;
@@ -74,6 +76,10 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
void constrainOpWithReadfirstlane(MachineIRBuilder &B, MachineInstr &MI,
unsigned OpIdx) const;
+ void
+ constrainVgprDstOpWithReadfirstlane(MachineIRBuilder &B, MachineInstr &MI,
+ const OperandsMapper &OpdMapper) const;
+
bool applyMappingDynStackAlloc(MachineIRBuilder &B,
const OperandsMapper &OpdMapper,
MachineInstr &MI) const;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
index f3e561578363967..8c981f92c921272 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
@@ -49,21 +49,31 @@ define amdgpu_vs <5 x float> @test_5xf16_5xf32_add_ext_mul(<5 x half> inreg %x,
; GFX9-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s5
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v0, s0, v0
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s4
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v1, s1, v1
-; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v2, s2, v2
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, v0
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, v1
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v2
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s6, v3
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v1, s7, v4
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v2, s8, v5
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s9, v6
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v4, s10, v7
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v2, s2, v2
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s7, v0
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s8, v4
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s9, v1
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s6, v3
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s10, v2
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s0, v3
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s4, v0
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s4
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul:
@@ -90,23 +100,35 @@ define amdgpu_vs <6 x float> @test_6xf16_6xf32_add_ext_mul_rhs(<6 x half> inreg
; GFX9-FAST-DENORM-LABEL: test_6xf16_6xf32_add_ext_mul_rhs:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s5
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v0, s0, v0
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s4
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v1, s1, v1
-; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v2, s2, v2
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, v0
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, v1
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v2
-; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s6, v3
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v1, s7, v4
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v2, s8, v5
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s9, v6
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v4, s10, v7
-; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v5, s11, v8
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, v1
+; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v2, s2, v2
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, v2
+; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s7, v0
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s8, v4
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s9, v1
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s10, v5
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s6, v3
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s4, v0
+; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s11, v2
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s0, v3
+; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s5, v0
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s4
+; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v5, s5
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_6xf16_6xf32_add_ext_mul_rhs:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
index 34635b077cd92d0..2ee5907d5d187af 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
@@ -199,6 +199,10 @@ define amdgpu_ps <2 x float> @s_floor_f64(double inreg %x) {
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_add_f64 v[0:1], s[2:3], -v[0:1]
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX78-LABEL: s_floor_f64:
@@ -223,6 +227,10 @@ define amdgpu_ps <2 x float> @s_floor_f64_fneg(double inreg %x) {
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_add_f64 v[0:1], -s[2:3], -v[0:1]
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX78-LABEL: s_floor_f64_fneg:
@@ -248,6 +256,10 @@ define amdgpu_ps <2 x float> @s_floor_f64_fabs(double inreg %x) {
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_add_f64 v[0:1], |s[2:3]|, -v[0:1]
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX78-LABEL: s_floor_f64_fabs:
@@ -273,6 +285,10 @@ define amdgpu_ps <2 x float> @s_floor_f64_fneg_fabs(double inreg %x) {
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_add_f64 v[0:1], -|s[2:3]|, -v[0:1]
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX78-LABEL: s_floor_f64_fneg_fabs:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index 1c40f7992bfe14c..cc804197a3ba0b6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -1480,7 +1480,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_exp_f32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000
; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1
@@ -1503,7 +1504,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_exp_f32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000
; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1
@@ -1526,7 +1528,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_exp_f32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000
; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1
@@ -1545,7 +1548,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo
-; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_exp_f32_e32 v0, s0
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
;
@@ -1566,8 +1570,9 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_exp_f32_e32 v0, s0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
index c8165c40ef8e7b3..2285033cd158e72 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
@@ -158,6 +158,9 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
; GCN-NEXT: v_add_f16_e32 v0, v1, v0
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ; return to shader part epilog
main_body:
%l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float 0.0, float %i, float 0.0, i1 0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
index 3a3764f7435e7c2..19655c2d0232880 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
@@ -16,7 +16,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(s32) = G_FADD [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr_32(s32) = G_FADD [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[FADD]](s32), implicit $exec
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_FADD %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
index 5297df3bedf8f2e..3345376ccdcdd2a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
@@ -157,21 +157,23 @@ define amdgpu_kernel void @sdivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8
-; GFX8-NEXT: s_mov_b32 s3, s2
-; GFX8-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_sub_u32 s14, 0, s8
-; GFX8-NEXT: s_subb_u32 s15, 0, s9
+; GFX8-NEXT: v_readfirstlane_b32 s3, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, s3
+; GFX8-NEXT: s_mov_b32 s3, s2
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v2, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX8-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX8-NEXT: v_readfirstlane_b32 s10, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, s10
+; GFX8-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
+; GFX8-NEXT: s_sub_u32 s14, 0, s8
; GFX8-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s14, v3, 0
+; GFX8-NEXT: s_subb_u32 s15, 0, s9
; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s14, v4, v[1:2]
; GFX8-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s15, v3, v[1:2]
@@ -317,21 +319,23 @@ define amdgpu_kernel void @sdivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
-; GFX9-NEXT: s_mov_b32 s3, s2
-; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_u32 s14, 0, s8
-; GFX9-NEXT: s_subb_u32 s15, 0, s9
+; GFX9-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, s3
+; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v2, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX9-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX9-NEXT: v_readfirstlane_b32 s10, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s10
+; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
+; GFX9-NEXT: s_sub_u32 s14, 0, s8
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s14, v3, 0
+; GFX9-NEXT: s_subb_u32 s15, 0, s9
; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s14, v4, v[1:2]
; GFX9-NEXT: v_mul_hi_u32 v5, v3, v0
; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s15, v3, v[1:2]
@@ -468,23 +472,25 @@ define amdgpu_kernel void @sdivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX10-NEXT: s_add_u32 s8, s10, s12
; GFX10-NEXT: s_mov_b32 s13, s12
; GFX10-NEXT: s_addc_u32 s9, s11, s12
-; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8
-; GFX10-NEXT: s_sub_u32 s10, 0, s8
-; GFX10-NEXT: s_subb_u32 s11, 0, s9
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s3, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, s3
+; GFX10-NEXT: s_mov_b32 s3, s2
+; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX10-NEXT: v_readfirstlane_b32 s10, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v3, s10
+; GFX10-NEXT: s_sub_u32 s10, 0, s8
+; GFX10-NEXT: s_subb_u32 s11, 0, s9
; GFX10-NEXT: v_mul_lo_u32 v4, s10, v2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s14, s10, v3, 0
; GFX10-NEXT: v_mul_lo_u32 v5, s11, v3
@@ -1291,7 +1297,8 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_xor_b64 s[16:17], s[16:17], s[4:5]
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX8-NEXT: s_sub_u32 s18, 0, s12
; GFX8-NEXT: s_subb_u32 s19, 0, s13
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -1299,7 +1306,8 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: v_trunc_f32_e32 v2, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX8-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, s0
; GFX8-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s18, v3, 0
; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s18, v4, v[1:2]
@@ -1418,7 +1426,8 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v0, vcc
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v14
; GFX8-NEXT: v_add_f32_e32 v0, v0, v5
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s5, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, s5
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v5, v1, v12, vcc
; GFX8-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7]
@@ -1427,7 +1436,8 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: v_trunc_f32_e32 v11, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0xcf800000, v11
; GFX8-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v12, v0
+; GFX8-NEXT: v_readfirstlane_b32 s5, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v12, s5
; GFX8-NEXT: s_sub_u32 s5, 0, s2
; GFX8-NEXT: s_subb_u32 s20, 0, s3
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
@@ -1602,7 +1612,8 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_xor_b64 s[16:17], s[16:17], s[4:5]
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX9-NEXT: s_sub_u32 s18, 0, s12
; GFX9-NEXT: s_subb_u32 s19, 0, s13
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -1610,7 +1621,8 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: v_trunc_f32_e32 v2, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX9-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s18, v3, 0
; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s18, v4, v[1:2]
@@ -1670,7 +1682,7 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: v_mul_lo_u32 v3, s16, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s16, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s17, v0
-; GFX9-NEXT: v_mul_hi_u32 v6, s17, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, s17, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
@@ -1682,38 +1694,38 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v0, v2
-; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s12, v5, 0
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v0, v2
+; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s12, v6, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT: v_add3_u32 v4, v3, v0, v6
+; GFX9-NEXT: v_add3_u32 v8, v3, v0, v5
; GFX9-NEXT: v_mov_b32_e32 v0, v2
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s12, v4, v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v6, s17
-; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, s16, v1
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s13, v5, v[2:3]
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s12, v8, v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v5, s17
+; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s16, v1
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], s13, v6, v[2:3]
; GFX9-NEXT: s_ashr_i32 s16, s3, 31
; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_subb_co_u32_e64 v6, s[0:1], v6, v2, vcc
-; GFX9-NEXT: v_sub_u32_e32 v1, s17, v2
-; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[0:1]
-; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v8
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6
-; GFX9-NEXT: v_subrev_co_u32_e32 v10, vcc, s12, v8
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v2, v3, s[0:1]
-; GFX9-NEXT: v_subbrev_co_u32_e64 v11, s[0:1], 0, v1, vcc
-; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], 1, v5
-; GFX9-NEXT: v_addc_co_u32_e64 v12, s[0:1], 0, v4, s[0:1]
+; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v5, v3, vcc
+; GFX9-NEXT: v_sub_u32_e32 v3, s17, v3
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v2
+; GFX9-NEXT: v_subrev_co_u32_e32 v10, vcc, s12, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v4, v5, s[0:1]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v11, s[0:1], 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], 1, v6
+; GFX9-NEXT: v_addc_co_u32_e64 v12, s[0:1], 0, v8, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v11
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v10
; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v11
-; GFX9-NEXT: v_cndmask_b32_e64 v13, v2, v13, s[0:1]
-; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v4, v13, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v5
; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v12, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s14, s6
; GFX9-NEXT: s_addc_u32 s1, s15, s6
@@ -1721,116 +1733,118 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_mov_b32 s17, s16
; GFX9-NEXT: s_addc_u32 s3, s3, s16
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v16, s2
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v7, vcc
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v16
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v7, vcc
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v16
+; GFX9-NEXT: v_readfirstlane_b32 s5, v4
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, s5
; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s12, v10
-; GFX9-NEXT: v_subbrev_co_u32_e32 v16, vcc, 0, v1, vcc
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
-; GFX9-NEXT: v_trunc_f32_e32 v17, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v17
-; GFX9-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v18, v1
+; GFX9-NEXT: v_subbrev_co_u32_e32 v16, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v4
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX9-NEXT: v_trunc_f32_e32 v17, v4
+; GFX9-NEXT: v_mul_f32_e32 v4, 0xcf800000, v17
+; GFX9-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s5, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v18, s5
; GFX9-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7]
; GFX9-NEXT: s_sub_u32 s5, 0, s2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
-; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s5, v18, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v13, v3, v14, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], s5, v18, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v5, v14, vcc
; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v17
; GFX9-NEXT: s_subb_u32 s20, 0, s3
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s5, v14, v[2:3]
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s5, v14, v[4:5]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v4, v12, s[0:1]
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[14:15], s20, v18, v[2:3]
-; GFX9-NEXT: v_mul_lo_u32 v3, v14, v1
; GFX9-NEXT: v_cndmask_b32_e32 v10, v11, v16, vcc
-; GFX9-NEXT: v_mul_lo_u32 v4, v18, v2
-; GFX9-NEXT: v_mul_hi_u32 v11, v18, v1
-; GFX9-NEXT: v_mul_hi_u32 v1, v14, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v13, s[0:1]
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v11
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX9-NEXT: v_mul_lo_u32 v11, v14, v2
-; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT: v_mul_hi_u32 v4, v18, v2
-; GFX9-NEXT: v_mul_hi_u32 v2, v14, v2
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v11, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
-; GFX9-NEXT: v_add_u32_e32 v4, v11, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v18, v1
-; GFX9-NEXT: v_add3_u32 v2, v4, v3, v2
-; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[14:15], s5, v11, 0
-; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v14, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v10, s[0:1]
-; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s5, v12, v[1:2]
-; GFX9-NEXT: v_xor_b32_e32 v8, s18, v5
-; GFX9-NEXT: v_xor_b32_e32 v9, s19, v9
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s20, v11, v[1:2]
-; GFX9-NEXT: v_mov_b32_e32 v10, s19
-; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s18, v8
-; GFX9-NEXT: v_xor_b32_e32 v5, s4, v7
-; GFX9-NEXT: v_mul_lo_u32 v7, v12, v3
-; GFX9-NEXT: v_mul_lo_u32 v8, v11, v4
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v9, v10, vcc
-; GFX9-NEXT: v_mul_hi_u32 v9, v11, v3
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[14:15], s20, v18, v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v12, s[0:1]
+; GFX9-NEXT: v_mul_lo_u32 v8, v14, v3
+; GFX9-NEXT: v_mul_lo_u32 v9, v18, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v18, v3
+; GFX9-NEXT: v_mul_hi_u32 v3, v14, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v1, v7, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v11
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
-; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX9-NEXT: v_mul_lo_u32 v9, v12, v4
-; GFX9-NEXT: v_mul_hi_u32 v3, v12, v3
-; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
-; GFX9-NEXT: v_mul_hi_u32 v8, v11, v4
-; GFX9-NEXT: v_mul_hi_u32 v4, v12, v4
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v9, v3
+; GFX9-NEXT: v_mul_lo_u32 v11, v14, v4
+; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
+; GFX9-NEXT: v_mul_hi_u32 v9, v18, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v14, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v11, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v9
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
+; GFX9-NEXT: v_add_u32_e32 v9, v11, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
-; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
+; GFX9-NEXT: v_add3_u32 v4, v9, v8, v4
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v18, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v4, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[14:15], s5, v8, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v13, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, v10, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
+; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s5, v9, v[1:2]
+; GFX9-NEXT: v_xor_b32_e32 v11, s19, v5
+; GFX9-NEXT: v_xor_b32_e32 v6, s18, v6
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s20, v8, v[1:2]
+; GFX9-NEXT: v_mov_b32_e32 v12, s19
+; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s18, v6
+; GFX9-NEXT: v_xor_b32_e32 v5, s4, v7
+; GFX9-NEXT: v_mul_lo_u32 v6, v9, v3
+; GFX9-NEXT: v_mul_lo_u32 v7, v8, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v11, v12, vcc
+; GFX9-NEXT: v_mul_hi_u32 v11, v8, v3
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX9-NEXT: v_add3_u32 v4, v8, v7, v4
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v11, v9, v4
+; GFX9-NEXT: v_mul_hi_u32 v3, v9, v3
+; GFX9-NEXT: v_add_u32_e32 v6, v7, v6
+; GFX9-NEXT: v_mul_hi_u32 v7, v8, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v9, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v11, v3
-; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v12, v4, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, s13, v3
-; GFX9-NEXT: v_mul_lo_u32 v8, s12, v4
-; GFX9-NEXT: v_mul_hi_u32 v10, s12, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT: v_add_u32_e32 v7, v11, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX9-NEXT: v_add3_u32 v4, v7, v6, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, s13, v3
+; GFX9-NEXT: v_mul_lo_u32 v7, s12, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, s12, v3
; GFX9-NEXT: v_mul_hi_u32 v3, s13, v3
-; GFX9-NEXT: v_mul_hi_u32 v12, s13, v4
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10
+; GFX9-NEXT: v_mul_hi_u32 v13, s13, v4
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX9-NEXT: v_mul_lo_u32 v10, s13, v4
-; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
-; GFX9-NEXT: v_mul_hi_u32 v8, s12, v4
-; GFX9-NEXT: v_xor_b32_e32 v6, s4, v6
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v10, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v3, v7
-; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], s2, v11, 0
-; GFX9-NEXT: v_mov_b32_e32 v9, s4
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v9, s13, v4
+; GFX9-NEXT: v_add_u32_e32 v6, v7, v6
+; GFX9-NEXT: v_mul_hi_u32 v7, s12, v4
+; GFX9-NEXT: v_xor_b32_e32 v10, s4, v10
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v9, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v3, v6
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], s2, v11, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX9-NEXT: v_add_u32_e32 v7, v9, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s4, v5
-; GFX9-NEXT: v_add_u32_e32 v8, v10, v8
-; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc
-; GFX9-NEXT: v_add3_u32 v9, v8, v7, v12
+; GFX9-NEXT: v_add3_u32 v9, v7, v12, v13
+; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v10, v8, vcc
; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[0:1], s2, v9, v[4:5]
; GFX9-NEXT: v_mov_b32_e32 v10, s13
; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s12, v3
@@ -1918,240 +1932,244 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
; GFX10-NEXT: s_mov_b32 s13, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
+; GFX10-NEXT: v_readfirstlane_b32 s5, v0
+; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX10-NEXT: s_sub_u32 s22, 0, s2
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
-; GFX10-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, s5
+; GFX10-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_readfirstlane_b32 s5, v0
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v2
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, s5
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v2, v2
-; GFX10-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v1
-; GFX10-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v5, v2
-; GFX10-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
-; GFX10-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX10-NEXT: v_mul_lo_u32 v7, s20, v5
-; GFX10-NEXT: v_trunc_f32_e32 v4, v4
-; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v0
-; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v4
-; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, s20, v6, 0
-; GFX10-NEXT: v_mul_lo_u32 v8, s21, v6
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v4
-; GFX10-NEXT: s_sub_u32 s5, 0, s2
-; GFX10-NEXT: s_subb_u32 s22, 0, s3
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
+; GFX10-NEXT: v_mul_f32_e32 v3, 0xcf800000, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, 0x2f800000, v1
+; GFX10-NEXT: v_add_f32_e32 v0, v3, v0
+; GFX10-NEXT: v_trunc_f32_e32 v3, v4
; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GFX10-NEXT: v_mul_lo_u32 v9, s5, v3
-; GFX10-NEXT: v_add3_u32 v7, v1, v7, v8
-; GFX10-NEXT: v_mul_lo_u32 v10, v5, v0
-; GFX10-NEXT: v_mul_hi_u32 v11, v6, v0
-; GFX10-NEXT: v_mad_u64_u32 v[1:2], s23, s5, v4, 0
-; GFX10-NEXT: v_mul_lo_u32 v8, s22, v4
-; GFX10-NEXT: v_mul_lo_u32 v12, v6, v7
-; GFX10-NEXT: v_mul_hi_u32 v0, v5, v0
-; GFX10-NEXT: v_mul_lo_u32 v13, v5, v7
-; GFX10-NEXT: v_mul_hi_u32 v14, v6, v7
-; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX10-NEXT: v_add3_u32 v2, v2, v9, v8
+; GFX10-NEXT: v_readfirstlane_b32 s5, v0
+; GFX10-NEXT: v_mul_f32_e32 v0, 0xcf800000, v3
+; GFX10-NEXT: v_mul_lo_u32 v6, s20, v4
+; GFX10-NEXT: v_cvt_u32_f32_e32 v5, s5
+; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX10-NEXT: v_add_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, s20, v5, 0
+; GFX10-NEXT: v_mul_lo_u32 v7, s21, v5
+; GFX10-NEXT: v_readfirstlane_b32 s5, v2
+; GFX10-NEXT: v_mul_lo_u32 v9, s22, v3
+; GFX10-NEXT: v_cvt_u32_f32_e32 v8, s5
+; GFX10-NEXT: s_subb_u32 s5, 0, s3
+; GFX10-NEXT: v_add3_u32 v6, v1, v6, v7
+; GFX10-NEXT: v_mul_lo_u32 v10, v4, v0
+; GFX10-NEXT: v_mul_hi_u32 v11, v5, v0
+; GFX10-NEXT: v_mad_u64_u32 v[1:2], s23, s22, v8, 0
+; GFX10-NEXT: v_mul_lo_u32 v7, s5, v8
+; GFX10-NEXT: v_mul_lo_u32 v12, v5, v6
+; GFX10-NEXT: v_mul_hi_u32 v0, v4, v0
+; GFX10-NEXT: v_mul_lo_u32 v13, v4, v6
+; GFX10-NEXT: v_mul_hi_u32 v14, v5, v6
+; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX10-NEXT: v_add3_u32 v2, v2, v9, v7
; GFX10-NEXT: v_add_co_u32 v10, s23, v10, v12
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s23
; GFX10-NEXT: v_add_co_u32 v0, s23, v13, v0
-; GFX10-NEXT: v_mul_lo_u32 v8, v3, v1
+; GFX10-NEXT: v_mul_lo_u32 v7, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s23
-; GFX10-NEXT: v_mul_lo_u32 v15, v4, v2
+; GFX10-NEXT: v_mul_lo_u32 v15, v8, v2
; GFX10-NEXT: v_add_co_u32 v10, s23, v10, v11
-; GFX10-NEXT: v_mul_hi_u32 v9, v4, v1
+; GFX10-NEXT: v_mul_hi_u32 v9, v8, v1
; GFX10-NEXT: v_mul_hi_u32 v1, v3, v1
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s23
; GFX10-NEXT: v_add_co_u32 v0, s23, v0, v14
; GFX10-NEXT: v_mul_lo_u32 v14, v3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s23
; GFX10-NEXT: v_add_nc_u32_e32 v10, v12, v10
-; GFX10-NEXT: v_add_co_u32 v8, s23, v8, v15
+; GFX10-NEXT: v_add_co_u32 v7, s23, v7, v15
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s23
-; GFX10-NEXT: v_mul_hi_u32 v16, v4, v2
+; GFX10-NEXT: v_mul_hi_u32 v16, v8, v2
; GFX10-NEXT: v_add_nc_u32_e32 v11, v13, v11
; GFX10-NEXT: v_add_co_u32 v1, s23, v14, v1
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s23
; GFX10-NEXT: v_add_co_u32 v0, s23, v0, v10
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s23
-; GFX10-NEXT: v_add_co_u32 v8, s23, v8, v9
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s23
+; GFX10-NEXT: v_add_co_u32 v7, s23, v7, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s23
; GFX10-NEXT: v_add_co_u32 v9, s23, v1, v16
-; GFX10-NEXT: v_add3_u32 v7, v11, v10, v7
+; GFX10-NEXT: v_add3_u32 v6, v11, v10, v6
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s23
-; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v6, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v8, v12, v8
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v5, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v12, v7
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v2, v3, v2
; GFX10-NEXT: v_add_nc_u32_e32 v10, v13, v1
-; GFX10-NEXT: v_mad_u64_u32 v[0:1], s23, s20, v6, 0
-; GFX10-NEXT: v_add_co_u32 v7, s23, v9, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s23
-; GFX10-NEXT: v_mul_lo_u32 v9, s21, v6
-; GFX10-NEXT: v_mul_lo_u32 v11, s20, v5
-; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v7
-; GFX10-NEXT: v_add3_u32 v2, v10, v8, v2
-; GFX10-NEXT: v_mul_lo_u32 v8, v5, v0
-; GFX10-NEXT: v_mul_hi_u32 v10, v6, v0
-; GFX10-NEXT: v_mul_hi_u32 v0, v5, v0
-; GFX10-NEXT: v_add3_u32 v7, v1, v11, v9
+; GFX10-NEXT: v_mad_u64_u32 v[0:1], s23, s20, v5, 0
+; GFX10-NEXT: v_add_co_u32 v6, s23, v9, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s23
+; GFX10-NEXT: v_mul_lo_u32 v9, s21, v5
+; GFX10-NEXT: v_mul_lo_u32 v11, s20, v4
+; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v8, v6
+; GFX10-NEXT: v_add3_u32 v2, v10, v7, v2
+; GFX10-NEXT: v_mul_lo_u32 v7, v4, v0
+; GFX10-NEXT: v_mul_hi_u32 v10, v5, v0
+; GFX10-NEXT: v_mul_hi_u32 v0, v4, v0
+; GFX10-NEXT: v_add3_u32 v8, v1, v11, v9
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v2, vcc_lo
-; GFX10-NEXT: v_mad_u64_u32 v[1:2], s20, s5, v4, 0
-; GFX10-NEXT: v_mul_lo_u32 v12, v6, v7
-; GFX10-NEXT: v_mul_lo_u32 v9, s22, v4
-; GFX10-NEXT: v_mul_lo_u32 v11, s5, v3
-; GFX10-NEXT: v_mul_lo_u32 v13, v5, v7
-; GFX10-NEXT: v_mul_hi_u32 v14, v6, v7
-; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX10-NEXT: v_mad_u64_u32 v[1:2], s20, s22, v6, 0
+; GFX10-NEXT: v_mul_lo_u32 v12, v5, v8
+; GFX10-NEXT: v_mul_lo_u32 v9, s5, v6
+; GFX10-NEXT: v_mul_lo_u32 v11, s22, v3
+; GFX10-NEXT: v_mul_lo_u32 v13, v4, v8
+; GFX10-NEXT: v_mul_hi_u32 v14, v5, v8
+; GFX10-NEXT: v_mul_hi_u32 v8, v4, v8
; GFX10-NEXT: v_mul_lo_u32 v15, v3, v1
-; GFX10-NEXT: v_mul_hi_u32 v16, v4, v1
-; GFX10-NEXT: v_add_co_u32 v8, s5, v8, v12
+; GFX10-NEXT: v_mul_hi_u32 v16, v6, v1
+; GFX10-NEXT: v_add_co_u32 v7, s5, v7, v12
; GFX10-NEXT: v_add3_u32 v2, v2, v11, v9
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v0, s5, v13, v0
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s5
-; GFX10-NEXT: v_add_co_u32 v8, s5, v8, v10
-; GFX10-NEXT: v_mul_lo_u32 v12, v4, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
+; GFX10-NEXT: v_add_co_u32 v7, s5, v7, v10
+; GFX10-NEXT: v_mul_lo_u32 v12, v6, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v0, s5, v0, v14
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s5
; GFX10-NEXT: v_mul_hi_u32 v1, v3, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v8, v9, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v9, v7
; GFX10-NEXT: v_mul_lo_u32 v13, v3, v2
-; GFX10-NEXT: v_mul_hi_u32 v14, v4, v2
+; GFX10-NEXT: v_mul_hi_u32 v14, v6, v2
; GFX10-NEXT: v_add_nc_u32_e32 v9, v11, v10
; GFX10-NEXT: v_add_co_u32 v10, s5, v15, v12
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s5
-; GFX10-NEXT: v_add_co_u32 v0, s5, v0, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
+; GFX10-NEXT: v_add_co_u32 v0, s5, v0, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v1, s5, v13, v1
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v10, s5, v10, v16
-; GFX10-NEXT: v_add3_u32 v7, v9, v8, v7
+; GFX10-NEXT: v_add3_u32 v7, v9, v7, v8
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s5
; GFX10-NEXT: v_add_co_u32 v1, s5, v1, v14
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0
+; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v11, v10
-; GFX10-NEXT: v_mul_hi_u32 v9, s0, v0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v7, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v5, v11, v10
+; GFX10-NEXT: v_mul_hi_u32 v2, v3, v2
; GFX10-NEXT: v_add_nc_u32_e32 v7, v12, v8
; GFX10-NEXT: v_mul_lo_u32 v8, s1, v0
-; GFX10-NEXT: v_mul_lo_u32 v10, s0, v5
+; GFX10-NEXT: v_mul_lo_u32 v10, s0, v4
+; GFX10-NEXT: v_add_co_u32 v1, s5, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
+; GFX10-NEXT: v_mul_hi_u32 v9, s0, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s1, v0
-; GFX10-NEXT: v_mul_lo_u32 v11, s1, v5
-; GFX10-NEXT: v_add_co_u32 v1, s5, v1, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s5
-; GFX10-NEXT: v_mul_hi_u32 v12, s0, v5
-; GFX10-NEXT: v_mul_hi_u32 v2, v3, v2
-; GFX10-NEXT: v_add_co_u32 v8, s5, v8, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s5
+; GFX10-NEXT: v_mul_lo_u32 v11, s1, v4
+; GFX10-NEXT: v_mul_hi_u32 v12, s0, v4
+; GFX10-NEXT: v_add3_u32 v2, v7, v5, v2
+; GFX10-NEXT: v_add_co_u32 v5, s5, v8, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s5
+; GFX10-NEXT: v_mul_hi_u32 v4, s1, v4
+; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v6, v1
+; GFX10-NEXT: v_add_co_u32 v5, s20, v5, v9
; GFX10-NEXT: v_add_co_u32 v0, s5, v11, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s5
-; GFX10-NEXT: v_add_co_u32 v8, s5, v8, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s20
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
+; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v2, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, s5, v0, v12
+; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s5
-; GFX10-NEXT: v_mul_hi_u32 v5, s1, v5
-; GFX10-NEXT: v_add_nc_u32_e32 v8, v10, v8
-; GFX10-NEXT: v_add3_u32 v2, v7, v6, v2
-; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v4, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v11, v9
-; GFX10-NEXT: v_add_co_u32 v7, s5, v0, v8
+; GFX10-NEXT: v_mul_lo_u32 v6, s15, v1
+; GFX10-NEXT: v_mul_hi_u32 v7, s14, v1
+; GFX10-NEXT: v_mul_hi_u32 v11, s14, v2
+; GFX10-NEXT: v_add_co_u32 v5, s5, v0, v5
+; GFX10-NEXT: v_add_nc_u32_e32 v3, v8, v9
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s5
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v2, vcc_lo
-; GFX10-NEXT: v_mul_lo_u32 v8, s7, v7
-; GFX10-NEXT: v_mul_lo_u32 v3, s15, v4
-; GFX10-NEXT: v_add3_u32 v5, v6, v0, v5
-; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, s6, v7, 0
-; GFX10-NEXT: v_mul_lo_u32 v6, s14, v2
-; GFX10-NEXT: v_mul_hi_u32 v10, s14, v4
-; GFX10-NEXT: v_mul_lo_u32 v9, s6, v5
-; GFX10-NEXT: v_mul_hi_u32 v4, s15, v4
-; GFX10-NEXT: v_mul_lo_u32 v11, s15, v2
-; GFX10-NEXT: v_add_co_u32 v3, s5, v3, v6
-; GFX10-NEXT: v_add3_u32 v1, v1, v9, v8
-; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, s0, v0
-; GFX10-NEXT: v_add_co_u32 v0, s0, v7, 1
-; GFX10-NEXT: v_sub_nc_u32_e32 v9, s1, v1
-; GFX10-NEXT: v_add_co_ci_u32_e64 v8, s0, 0, v5, s0
-; GFX10-NEXT: v_sub_co_ci_u32_e64 v12, s0, s1, v1, vcc_lo
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e64 s0, s6, v6
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, 1, s5
-; GFX10-NEXT: v_add_co_u32 v4, s1, v11, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v14, vcc_lo, v6, s6
-; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s0, 0, v9, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s7, v12
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
+; GFX10-NEXT: v_mul_lo_u32 v8, s14, v2
+; GFX10-NEXT: v_mul_lo_u32 v9, s7, v5
+; GFX10-NEXT: v_add3_u32 v3, v3, v0, v4
+; GFX10-NEXT: v_mul_hi_u32 v4, s15, v1
+; GFX10-NEXT: v_mad_u64_u32 v[0:1], s5, s6, v5, 0
+; GFX10-NEXT: v_add_co_u32 v6, s5, v6, v8
+; GFX10-NEXT: v_mul_lo_u32 v10, s6, v3
+; GFX10-NEXT: v_mul_lo_u32 v8, s15, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s5
+; GFX10-NEXT: v_add_co_u32 v6, s5, v6, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s5
+; GFX10-NEXT: v_mul_hi_u32 v2, s15, v2
+; GFX10-NEXT: v_add3_u32 v1, v1, v10, v9
+; GFX10-NEXT: v_add_co_u32 v4, s5, v8, v4
+; GFX10-NEXT: v_sub_co_u32 v9, vcc_lo, s0, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v8, s1, v1
+; GFX10-NEXT: v_sub_co_ci_u32_e64 v10, s0, s1, v1, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v12, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s5
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s7, v8, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s6, v9
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v9, s6
+; GFX10-NEXT: v_subrev_co_ci_u32_e64 v12, s0, 0, v0, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e64 s0, s7, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
+; GFX10-NEXT: v_cmp_le_u32_e64 s0, s6, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0
+; GFX10-NEXT: v_cmp_le_u32_e64 s0, s7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, -1, s0
+; GFX10-NEXT: v_add_co_u32 v16, s0, v5, 1
+; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v3, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s7, v10
; GFX10-NEXT: v_cndmask_b32_e64 v1, v13, v1, s0
-; GFX10-NEXT: v_cmp_le_u32_e64 s0, s6, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v15, v14, s0
+; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX10-NEXT: v_add_co_u32 v14, s0, v16, 1
+; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v17, s0
+; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
+; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v13
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v11, vcc_lo, s7, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
-; GFX10-NEXT: v_cmp_le_u32_e64 s0, s7, v15
-; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, -1, s0
-; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v10
-; GFX10-NEXT: v_mul_hi_u32 v10, s14, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s7, v15
-; GFX10-NEXT: v_mul_hi_u32 v2, s15, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v17, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v16, v13, s0
-; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX10-NEXT: v_add_co_u32 v16, s0, v0, 1
-; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v8, s0
-; GFX10-NEXT: v_add_co_u32 v3, s0, v4, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v10, v13, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v11
-; GFX10-NEXT: v_mul_lo_u32 v13, s3, v3
-; GFX10-NEXT: v_add3_u32 v2, v10, v4, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v0, v16, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v17, s0
-; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, s2, v3, 0
-; GFX10-NEXT: v_mul_lo_u32 v8, s2, v2
-; GFX10-NEXT: v_sub_co_u32 v10, s1, v14, s6
-; GFX10-NEXT: v_subrev_co_ci_u32_e64 v9, s1, 0, v9, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v14, v10, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX10-NEXT: v_add3_u32 v1, v1, v8, v13
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v15, v9, s0
+; GFX10-NEXT: v_add3_u32 v2, v7, v6, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v17, v15, s0
+; GFX10-NEXT: v_mad_u64_u32 v[0:1], s1, s2, v4, 0
+; GFX10-NEXT: v_mul_lo_u32 v15, s3, v4
+; GFX10-NEXT: v_mul_lo_u32 v7, s2, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v16, v14, s0
+; GFX10-NEXT: v_sub_co_u32 v14, s1, v8, s6
+; GFX10-NEXT: v_subrev_co_ci_u32_e64 v11, s1, 0, v11, s1
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s0
+; GFX10-NEXT: v_add3_u32 v1, v1, v7, v15
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v11, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v3, s19, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, s0, s14, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s1, s15, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v1, s15, v1
-; GFX10-NEXT: v_xor_b32_e32 v0, s18, v7
+; GFX10-NEXT: v_xor_b32_e32 v0, s18, v5
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v9
-; GFX10-NEXT: v_xor_b32_e32 v4, s19, v4
-; GFX10-NEXT: v_xor_b32_e32 v5, s4, v5
; GFX10-NEXT: v_mov_b32_e32 v16, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v6, s4, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, vcc_lo, s3, v1, s0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v8
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v8, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v13, s0, 0, v10, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v0, s0, v0, s18
-; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s19, v4, s0
+; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s19, v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v9
-; GFX10-NEXT: v_xor_b32_e32 v4, s4, v6
+; GFX10-NEXT: v_xor_b32_e32 v3, s4, v7
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, v11, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v13
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v12
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
-; GFX10-NEXT: v_add_co_u32 v14, s0, v3, 1
+; GFX10-NEXT: v_add_co_u32 v14, s0, v4, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v2, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v13
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
@@ -2161,24 +2179,24 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_sub_co_u32 v7, s0, v12, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
; GFX10-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v6
+; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v14, v15, v17, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v12, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v13, v10, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v4, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v4, v11, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, v6, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v7, s0
; GFX10-NEXT: s_xor_b64 s[0:1], s[12:13], s[16:17]
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s4, v5, vcc_lo
-; GFX10-NEXT: v_xor_b32_e32 v3, s0, v3
-; GFX10-NEXT: v_xor_b32_e32 v8, s1, v2
-; GFX10-NEXT: v_xor_b32_e32 v6, s12, v6
+; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v3, s4
+; GFX10-NEXT: v_xor_b32_e32 v3, s0, v10
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s4, v6, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v6, s1, v2
+; GFX10-NEXT: v_xor_b32_e32 v8, s12, v8
; GFX10-NEXT: v_xor_b32_e32 v7, s12, v7
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v3, s0
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v8, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v6, s12
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
+; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v8, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s12, v7, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v16, v[0:3], s[8:9]
; GFX10-NEXT: global_store_dwordx4 v16, v[4:7], s[10:11]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
index 8b4e218f78948b2..35c8eb34a14d69e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
@@ -120,13 +120,15 @@ define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_subb_u32 s3, 0, s11
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v2, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX8-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, s0
; GFX8-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v3, 0
; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s2, v4, v[1:2]
@@ -259,13 +261,15 @@ define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX9-NEXT: s_subb_u32 s3, 0, s11
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v2, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX9-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v3, 0
; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s2, v4, v[1:2]
@@ -388,18 +392,20 @@ define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s11
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s10
-; GFX10-NEXT: s_sub_u32 s0, 0, s10
-; GFX10-NEXT: s_subb_u32 s1, 0, s11
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v3, s0
+; GFX10-NEXT: s_sub_u32 s0, 0, s10
+; GFX10-NEXT: s_subb_u32 s1, 0, s11
; GFX10-NEXT: v_mul_lo_u32 v4, s0, v2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v3, 0
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v3
@@ -991,13 +997,15 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_subb_u32 s3, 0, s13
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v2, v1
; GFX8-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX8-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, s0
; GFX8-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v3, 0
; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s2, v4, v[1:2]
@@ -1091,25 +1099,27 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s15
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v4, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s14
-; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s12, v8
-; GFX8-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
; GFX8-NEXT: v_subbrev_u32_e64 v11, s[0:1], 0, v5, vcc
+; GFX8-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, s0
; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v6
+; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v7, s[0:1]
; GFX8-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GFX8-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
; GFX8-NEXT: v_trunc_f32_e32 v14, v2
; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v14
-; GFX8-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX8-NEXT: v_cvt_u32_f32_e32 v15, v1
-; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v7, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v11
+; GFX8-NEXT: v_add_f32_e32 v1, v2, v1
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: v_cvt_u32_f32_e32 v15, s0
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v10
; GFX8-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[0:1]
-; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s2, v15, 0
; GFX8-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s2, v15, 0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v11
; GFX8-NEXT: v_cndmask_b32_e64 v16, v3, v16, s[0:1]
; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v14, v[2:3]
@@ -1259,14 +1269,16 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_subb_u32 s3, 0, s13
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, s0
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v2, v1
; GFX9-NEXT: v_mul_f32_e32 v1, 0xcf800000, v2
; GFX9-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s0
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v3, 0
; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s2, v4, v[1:2]
@@ -1360,25 +1372,27 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s15
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v3, v6, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s14
-; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
; GFX9-NEXT: v_subrev_co_u32_e32 v11, vcc, s12, v2
-; GFX9-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
; GFX9-NEXT: v_subbrev_co_u32_e64 v12, s[0:1], 0, v7, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX9-NEXT: v_readfirstlane_b32 s0, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, s0
; GFX9-NEXT: v_add_co_u32_e64 v13, s[0:1], 1, v8
+; GFX9-NEXT: v_addc_co_u32_e64 v14, s[0:1], 0, v9, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
; GFX9-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
; GFX9-NEXT: v_trunc_f32_e32 v15, v4
; GFX9-NEXT: v_mul_f32_e32 v4, 0xcf800000, v15
-; GFX9-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v16, v3
-; GFX9-NEXT: v_addc_co_u32_e64 v14, s[0:1], 0, v9, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v12
+; GFX9-NEXT: v_add_f32_e32 v3, v4, v3
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX9-NEXT: v_readfirstlane_b32 s0, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v16, s0
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v11
; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, -1, s[0:1]
-; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], s2, v16, 0
; GFX9-NEXT: v_cvt_u32_f32_e32 v15, v15
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[0:1], s2, v16, 0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v12
; GFX9-NEXT: v_cndmask_b32_e64 v17, v5, v17, s[0:1]
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[0:1], s2, v15, v[4:5]
@@ -1519,16 +1533,18 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s15
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s12
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s14
-; GFX10-NEXT: s_sub_u32 s0, 0, s12
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
-; GFX10-NEXT: s_subb_u32 s1, 0, s13
-; GFX10-NEXT: s_sub_u32 s2, 0, s14
-; GFX10-NEXT: s_subb_u32 s3, 0, s15
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, s0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, s1
+; GFX10-NEXT: s_sub_u32 s0, 0, s12
+; GFX10-NEXT: s_subb_u32 s1, 0, s13
+; GFX10-NEXT: s_sub_u32 s3, 0, s14
+; GFX10-NEXT: s_subb_u32 s16, 0, s15
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
@@ -1541,14 +1557,17 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_add_f32_e32 v0, v4, v0
; GFX10-NEXT: v_add_f32_e32 v1, v5, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GFX10-NEXT: v_mul_lo_u32 v10, s2, v6
-; GFX10-NEXT: v_cvt_u32_f32_e32 v5, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v8, v1
+; GFX10-NEXT: v_mul_lo_u32 v10, s3, v6
+; GFX10-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10-NEXT: v_readfirstlane_b32 s6, v1
; GFX10-NEXT: v_mul_lo_u32 v7, s0, v4
-; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, s0, v5, 0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v5, s2
+; GFX10-NEXT: v_cvt_u32_f32_e32 v8, s6
+; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
+; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v5, 0
; GFX10-NEXT: v_mul_lo_u32 v9, s1, v5
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s6, s2, v8, 0
-; GFX10-NEXT: v_mul_lo_u32 v11, s3, v8
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s2, s3, v8, 0
+; GFX10-NEXT: v_mul_lo_u32 v11, s16, v8
; GFX10-NEXT: v_add3_u32 v1, v1, v7, v9
; GFX10-NEXT: v_mul_lo_u32 v7, v4, v0
; GFX10-NEXT: v_mul_hi_u32 v9, v5, v0
@@ -1562,45 +1581,45 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_mul_hi_u32 v2, v6, v2
; GFX10-NEXT: v_mul_lo_u32 v16, v6, v3
; GFX10-NEXT: v_mul_hi_u32 v14, v5, v1
-; GFX10-NEXT: v_add_co_u32 v7, s6, v7, v12
-; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v0, s6, v13, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v10, s6, v10, v15
-; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v2, s6, v16, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v7, s6, v7, v9
+; GFX10-NEXT: v_add_co_u32 v7, s2, v7, v12
+; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v0, s2, v13, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v10, s2, v10, v15
+; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v2, s2, v16, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v7, s2, v7, v9
; GFX10-NEXT: v_mul_hi_u32 v17, v8, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v14
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v10, s6, v10, v11
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v0, s2, v0, v14
+; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v10, s2, v10, v11
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s2
; GFX10-NEXT: v_add_nc_u32_e32 v7, v12, v7
-; GFX10-NEXT: v_add_co_u32 v2, s6, v2, v17
+; GFX10-NEXT: v_add_co_u32 v2, s2, v2, v17
; GFX10-NEXT: v_mul_hi_u32 v1, v4, v1
; GFX10-NEXT: v_add_nc_u32_e32 v10, v15, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6
-; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
+; GFX10-NEXT: v_add_co_u32 v0, s2, v0, v7
; GFX10-NEXT: v_add_nc_u32_e32 v9, v13, v9
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s2
; GFX10-NEXT: v_mul_hi_u32 v3, v6, v3
-; GFX10-NEXT: v_add_co_u32 v2, s6, v2, v10
+; GFX10-NEXT: v_add_co_u32 v2, s2, v2, v10
; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v11
-; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s2
; GFX10-NEXT: v_add3_u32 v1, v9, v7, v1
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v5, v0
; GFX10-NEXT: v_add3_u32 v3, v11, v10, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v8, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v6, v3, vcc_lo
-; GFX10-NEXT: v_mad_u64_u32 v[0:1], s6, s0, v5, 0
+; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, s0, v5, 0
; GFX10-NEXT: v_mul_lo_u32 v7, s1, v5
; GFX10-NEXT: v_mul_lo_u32 v9, s0, v4
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, s2, v8, 0
-; GFX10-NEXT: v_mul_lo_u32 v10, s3, v8
-; GFX10-NEXT: v_mul_lo_u32 v11, s2, v6
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, s3, v8, 0
+; GFX10-NEXT: v_mul_lo_u32 v10, s16, v8
+; GFX10-NEXT: v_mul_lo_u32 v11, s3, v6
; GFX10-NEXT: v_mul_lo_u32 v12, v4, v0
; GFX10-NEXT: v_mul_hi_u32 v13, v5, v0
; GFX10-NEXT: v_mul_hi_u32 v0, v4, v0
@@ -1612,11 +1631,11 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_mul_lo_u32 v10, v5, v1
; GFX10-NEXT: v_mul_lo_u32 v11, v4, v1
; GFX10-NEXT: v_mul_hi_u32 v14, v5, v1
-; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
+; GFX10-NEXT: v_mul_hi_u32 v1, v4, v1
; GFX10-NEXT: v_mul_lo_u32 v15, v8, v3
; GFX10-NEXT: v_mul_lo_u32 v16, v6, v3
; GFX10-NEXT: v_mul_hi_u32 v17, v8, v3
-; GFX10-NEXT: v_mul_hi_u32 v1, v4, v1
+; GFX10-NEXT: v_mul_hi_u32 v3, v6, v3
; GFX10-NEXT: v_add_co_u32 v10, s0, v12, v10
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v11, v0
@@ -1638,68 +1657,73 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v7, v15, v7
-; GFX10-NEXT: v_mul_hi_u32 v3, v6, v3
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v5, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v10, v16, v10
; GFX10-NEXT: v_add3_u32 v1, v11, v9, v1
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v10, v16, v10
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mul_lo_u32 v4, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v5, s8, v0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
+; GFX10-NEXT: v_mul_lo_u32 v4, s9, v0
; GFX10-NEXT: v_add3_u32 v3, v10, v7, v3
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2
; GFX10-NEXT: v_mul_lo_u32 v7, s8, v1
; GFX10-NEXT: v_mul_hi_u32 v0, s9, v0
-; GFX10-NEXT: v_mul_lo_u32 v9, s9, v1
-; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2
+; GFX10-NEXT: v_mul_lo_u32 v8, s9, v1
+; GFX10-NEXT: v_mul_hi_u32 v10, s8, v1
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo
-; GFX10-NEXT: v_mul_hi_u32 v6, s8, v1
+; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX10-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v7
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
-; GFX10-NEXT: v_add_co_u32 v0, s0, v9, v0
+; GFX10-NEXT: v_add_co_u32 v0, s0, v8, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
-; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v6
+; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v10
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
-; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX10-NEXT: v_mul_hi_u32 v9, s10, v2
; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v4
-; GFX10-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX10-NEXT: v_mul_lo_u32 v7, s10, v3
+; GFX10-NEXT: v_mul_hi_u32 v2, s11, v2
+; GFX10-NEXT: v_mul_lo_u32 v10, s11, v3
; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5
-; GFX10-NEXT: v_mul_hi_u32 v8, s10, v2
; GFX10-NEXT: v_add_co_u32 v4, s0, v0, v4
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_mul_hi_u32 v2, s11, v2
-; GFX10-NEXT: v_mul_lo_u32 v9, s11, v3
-; GFX10-NEXT: v_mul_hi_u32 v10, s10, v3
+; GFX10-NEXT: v_mul_hi_u32 v8, s10, v3
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7
-; GFX10-NEXT: v_add3_u32 v5, v5, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
+; GFX10-NEXT: v_add3_u32 v5, v5, v0, v1
+; GFX10-NEXT: v_add_co_u32 v2, s0, v10, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s12, v4, 0
; GFX10-NEXT: v_mul_lo_u32 v11, s13, v4
; GFX10-NEXT: v_mul_lo_u32 v12, s12, v5
-; GFX10-NEXT: v_add_co_u32 v2, s0, v9, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v8
+; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v9
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
-; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v10
+; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v8
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX10-NEXT: v_add3_u32 v1, v1, v12, v11
; GFX10-NEXT: v_add_nc_u32_e32 v6, v7, v6
-; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3
-; GFX10-NEXT: v_mov_b32_e32 v10, 0
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v9, v8
+; GFX10-NEXT: v_mov_b32_e32 v9, 0
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v8
+; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, s8, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s9, v1
-; GFX10-NEXT: v_sub_co_u32 v9, vcc_lo, s8, v0
+; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s0, s9, v1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v0, vcc_lo, s13, v8, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v9
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s12, v10
+; GFX10-NEXT: v_add3_u32 v3, v7, v6, v3
+; GFX10-NEXT: v_mul_lo_u32 v19, s15, v2
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v9, s12
+; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v10, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v12, s0, 0, v0, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s13, v11
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s13, v0, vcc_lo
+; GFX10-NEXT: v_mul_lo_u32 v7, s14, v3
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s12, v8
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0
@@ -1711,65 +1735,59 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s13, v12
; GFX10-NEXT: v_cndmask_b32_e64 v14, v15, v14, s0
-; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v6
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: v_add_co_u32 v6, s0, v16, 1
-; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v17, s0
-; GFX10-NEXT: v_add3_u32 v3, v7, v1, v3
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s13, v0, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v15, s0, v16, 1
+; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v17, s0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, s14, v2, 0
-; GFX10-NEXT: v_mul_lo_u32 v18, s14, v3
-; GFX10-NEXT: v_mul_lo_u32 v19, s15, v2
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX10-NEXT: v_sub_co_u32 v14, s0, v8, s12
-; GFX10-NEXT: v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v16, v6, vcc_lo
+; GFX10-NEXT: v_subrev_co_ci_u32_e64 v6, s0, 0, v6, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc_lo
+; GFX10-NEXT: v_add3_u32 v7, v1, v7, v19
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v13
-; GFX10-NEXT: v_add3_u32 v16, v1, v18, v19
-; GFX10-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v13, s1, s10, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v6, s0
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, s11, v16
-; GFX10-NEXT: v_sub_co_ci_u32_e64 v17, s2, s11, v16, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v15, s0
+; GFX10-NEXT: v_sub_co_ci_u32_e64 v17, s2, s11, v7, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v15, s0
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, s11, v7
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v16, s0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v14, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v17
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s1, s15, v4, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s14, v13
-; GFX10-NEXT: v_cmp_le_u32_e64 s2, s15, v17
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, -1, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s15, v17
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v9, v5, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s1
; GFX10-NEXT: v_sub_co_u32 v15, s1, v13, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v16, s2, 0, v8, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v14, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s15, v16
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s14, v15
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v2, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s15, v16
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
-; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v12, 1
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v12, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, 0, v14, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, vcc_lo, s15, v8, s1
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
-; GFX10-NEXT: v_sub_co_u32 v6, s1, v15, s14
+; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7
+; GFX10-NEXT: v_sub_co_u32 v7, s1, v15, s14
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s1, 0, v8, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v12, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v18, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v7, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v9, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v6, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v12, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v13, v6, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v13, v7, s1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v17, v8, s1
-; GFX10-NEXT: global_store_dwordx4 v10, v[0:3], s[4:5]
-; GFX10-NEXT: global_store_dwordx4 v10, v[4:7], s[6:7]
+; GFX10-NEXT: global_store_dwordx4 v9, v[0:3], s[4:5]
+; GFX10-NEXT: global_store_dwordx4 v9, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm
%div = udiv <2 x i64> %x, %y
store <2 x i64> %div, ptr addrspace(1) %out0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
index c8570d6f279a6b2..88cdb7296b604e8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
@@ -47,8 +47,8 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-LABEL: s_exp_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dword s2, s[0:1], 0x2c
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x39a3b295
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s3, s2, 0xfffff000
@@ -56,17 +56,20 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v1, s3, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: v_rndne_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v1, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
@@ -118,12 +121,13 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v3
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, s3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v1, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
@@ -166,7 +170,6 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0
; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2
@@ -174,17 +177,19 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3
; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v3
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, s3
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -391,38 +396,44 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-GISEL-LABEL: s_exp_v2f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x39a3b295
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8a000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s5, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s4, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v3, s4
; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s4
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v5, s3, v5
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x39a3b295, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3fb8a000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v0
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v5
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v0
-; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_rndne_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v5, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v2, v3, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b17218
@@ -496,14 +507,16 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v5
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v4
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, s4
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, s4
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v3, v2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
@@ -577,14 +590,16 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v5
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v4
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, s4
; SI-GISEL-NEXT: v_add_f32_e32 v0, v5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v5, s4
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v3, v2
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
@@ -928,8 +943,8 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-LABEL: s_exp_v3f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x39a3b295
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
@@ -937,48 +952,57 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v0, s4, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v1
; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s2, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_rndne_f32_e32 v0, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v3, s2
; VI-GISEL-NEXT: s_and_b32 s2, s5, 0xfffff000
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s2
; VI-GISEL-NEXT: v_sub_f32_e32 v5, s5, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3fb8a000, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, s2, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0
-; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s2, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v5, s3, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v5
+; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v6
+; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v5
+; VI-GISEL-NEXT: v_exp_f32_e32 v6, s2
; VI-GISEL-NEXT: s_and_b32 s2, s6, 0xfffff000
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_ldexp_f32 v5, v5, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_ldexp_f32 v5, v6, v5
; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v6, s6, v6
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x39a3b295, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
-; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s3, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v3, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2ce8ed0
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42b17218
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v6
-; VI-GISEL-NEXT: v_exp_f32_e32 v6, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v6, s2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v4
@@ -1057,35 +1081,38 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f
; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s5, v1
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s5, v1, -v5
-; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v5
-; GFX900-GISEL-NEXT: v_fma_f32 v6, s5, v2, v6
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
-; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s4, v1
; GFX900-GISEL-NEXT: v_fma_f32 v3, s4, v1, -v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s5, v1
; GFX900-GISEL-NEXT: v_fma_f32 v3, s4, v2, v3
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v6, s5, v1, -v5
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v5
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v5, v6
+; GFX900-GISEL-NEXT: v_fma_f32 v6, s5, v2, v6
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, s2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v5
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v7
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, s2
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
+; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v6, v5
; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s6, v1
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_fma_f32 v1, s6, v1, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v1, s6, v2, v1
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v6
; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v3, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, s2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
@@ -1164,37 +1191,40 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f
; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_mul_f32_e32 v5, s5, v1
-; SI-GISEL-NEXT: v_fma_f32 v6, s5, v1, -v5
-; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v5
-; SI-GISEL-NEXT: v_fma_f32 v6, s5, v2, v6
-; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
-; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
; SI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v1
; SI-GISEL-NEXT: v_fma_f32 v3, s4, v1, -v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, s5, v1
; SI-GISEL-NEXT: v_fma_f32 v3, s4, v2, v3
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
+; SI-GISEL-NEXT: v_fma_f32 v6, s5, v1, -v5
+; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v5
; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v5, v6
+; SI-GISEL-NEXT: v_fma_f32 v6, s5, v2, v6
+; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, s2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v5
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v5, v7
+; SI-GISEL-NEXT: v_exp_f32_e32 v6, s2
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v4
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v6, v5
; SI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v1
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_fma_f32 v1, s6, v1, -v6
; SI-GISEL-NEXT: v_fma_f32 v1, s6, v2, v1
; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v6
; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
; SI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v3
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v3, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42b17218
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
-; SI-GISEL-NEXT: v_exp_f32_e32 v6, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v6, s2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
@@ -1207,7 +1237,7 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v4
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s6, v3
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
@@ -1691,8 +1721,8 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-LABEL: s_exp_v4f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8a000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x39a3b295
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3fb8a000
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x42b17218
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -1701,67 +1731,79 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v0, s4, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, s2, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0
-; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_rndne_f32_e32 v0, v1
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, s2
; VI-GISEL-NEXT: s_and_b32 s2, s5, 0xfffff000
; VI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v1, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s2
; VI-GISEL-NEXT: v_sub_f32_e32 v1, s5, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x39a3b295, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v7, s2, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v7, v1
-; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; VI-GISEL-NEXT: v_rndne_f32_e32 v1, v6
+; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v6, s2
; VI-GISEL-NEXT: s_and_b32 s2, s6, 0xfffff000
; VI-GISEL-NEXT: v_mul_f32_e32 v8, s2, v2
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
-; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v6, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
; VI-GISEL-NEXT: v_sub_f32_e32 v6, s6, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3fb8a000, v6
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v9
-; VI-GISEL-NEXT: v_mul_f32_e32 v9, s2, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v9, v6
-; VI-GISEL-NEXT: v_rndne_f32_e32 v9, v8
-; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v9
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v8, v6
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; VI-GISEL-NEXT: v_exp_f32_e32 v6, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s3, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v8
+; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v8, s2, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v6
+; VI-GISEL-NEXT: v_exp_f32_e32 v8, s2
; VI-GISEL-NEXT: s_and_b32 s2, s7, 0xfffff000
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
-; VI-GISEL-NEXT: v_ldexp_f32 v6, v6, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v6, v8, v6
; VI-GISEL-NEXT: v_mov_b32_e32 v8, s2
; VI-GISEL-NEXT: v_sub_f32_e32 v8, s7, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x39a3b295, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3fb8a000, v8
; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
-; VI-GISEL-NEXT: v_rndne_f32_e32 v8, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v8
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s3, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; VI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v4
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v8
-; VI-GISEL-NEXT: v_exp_f32_e32 v8, v2
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v8, s2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s5, v5
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
@@ -1860,43 +1902,47 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v1, s4, v3, v1
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v4
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, s2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v1, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s5, v2
; GFX900-GISEL-NEXT: v_fma_f32 v6, s5, v2, -v1
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v1
; GFX900-GISEL-NEXT: v_fma_f32 v6, s5, v3, v6
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v7
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, s2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v5
-; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v6, v1
; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s6, v2
; GFX900-GISEL-NEXT: v_fma_f32 v8, s6, v2, -v6
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v9, v6
; GFX900-GISEL-NEXT: v_fma_f32 v8, s6, v3, v8
; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v9
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, s2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v4
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v8, v6
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, s7, v2
; GFX900-GISEL-NEXT: v_fma_f32 v2, s7, v2, -v8
; GFX900-GISEL-NEXT: v_fma_f32 v2, s7, v3, v2
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v8
; GFX900-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v8, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, s2
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s5, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v4
@@ -1994,44 +2040,48 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v1, s4, v3, v1
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v4
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, s2
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v4
-; SI-GISEL-NEXT: s_mov_b32 s2, -1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_mul_f32_e32 v1, s5, v2
; SI-GISEL-NEXT: v_fma_f32 v6, s5, v2, -v1
; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v1
; SI-GISEL-NEXT: v_fma_f32 v6, s5, v3, v6
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v7
+; SI-GISEL-NEXT: v_exp_f32_e32 v6, s2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v5
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v6, v1
; SI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v2
; SI-GISEL-NEXT: v_fma_f32 v8, s6, v2, -v6
; SI-GISEL-NEXT: v_rndne_f32_e32 v9, v6
; SI-GISEL-NEXT: v_fma_f32 v8, s6, v3, v8
; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9
; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9
-; SI-GISEL-NEXT: v_exp_f32_e32 v6, v6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v9
+; SI-GISEL-NEXT: v_exp_f32_e32 v8, s2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v4
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v6, v8
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v8, v6
; SI-GISEL-NEXT: v_mul_f32_e32 v8, s7, v2
; SI-GISEL-NEXT: v_fma_f32 v2, s7, v2, -v8
; SI-GISEL-NEXT: v_fma_f32 v2, s7, v3, v2
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v8
; SI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3
; SI-GISEL-NEXT: v_add_f32_e32 v2, v8, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
-; SI-GISEL-NEXT: v_exp_f32_e32 v8, v2
+; SI-GISEL-NEXT: v_exp_f32_e32 v8, s2
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s5, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v4
@@ -2043,7 +2093,7 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s7, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -5243,21 +5293,24 @@ define float @v_exp_f32_undef() {
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_sub_f32_e64 v0, s4, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x39a3b295
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x39a3b295
; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
-; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
-; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_rndne_f32_e32 v0, v1
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v1, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
@@ -5293,10 +5346,11 @@ define float @v_exp_f32_undef() {
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, s4
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v1, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
@@ -5332,10 +5386,11 @@ define float @v_exp_f32_undef() {
; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v2
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, s4
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index 587109b9431a1a5..a9e5c217bc945d2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -40,7 +40,8 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, s2
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; SI-GISEL-NEXT: s_mov_b32 s2, -1
@@ -77,7 +78,8 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1
@@ -114,7 +116,8 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
@@ -204,13 +207,15 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; SI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, s0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; SI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
-; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, s2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
; SI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
@@ -252,13 +257,15 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v3, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
-; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, s2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
; VI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
@@ -299,13 +306,15 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, s0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, s2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
@@ -421,21 +430,24 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; SI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, s2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v1
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
+; SI-GISEL-NEXT: s_mov_b32 s10, -1
; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
; SI-GISEL-NEXT: v_add_f32_e32 v4, s5, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; SI-GISEL-NEXT: v_exp_f32_e32 v4, s0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
-; SI-GISEL-NEXT: v_exp_f32_e32 v4, v4
; SI-GISEL-NEXT: v_add_f32_e32 v1, s6, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v2, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v2, s2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
; SI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
-; SI-GISEL-NEXT: s_mov_b32 s10, -1
; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000
; SI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
@@ -476,7 +488,6 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-LABEL: s_exp2_v3f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
-; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
@@ -484,21 +495,26 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; VI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, s2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v1
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
+; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v4, s5, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_exp_f32_e32 v4, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v1, s6, v1
-; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
-; VI-GISEL-NEXT: v_exp_f32_e32 v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v2, s4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
; VI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
@@ -537,7 +553,6 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL-LABEL: s_exp2_v3f32:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
@@ -545,22 +560,27 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s5, v1
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v4, s5, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, s0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s6, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s6, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, v4
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, s4
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm
;
@@ -692,39 +712,43 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
;
; SI-GISEL-LABEL: s_exp2_v4f32:
; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
-; SI-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
+; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
-; SI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, s0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, s2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
+; SI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; SI-GISEL-NEXT: v_exp_f32_e32 v5, s0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
-; SI-GISEL-NEXT: v_add_f32_e32 v5, s6, v5
-; SI-GISEL-NEXT: v_add_f32_e32 v2, s7, v2
-; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; SI-GISEL-NEXT: v_exp_f32_e32 v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_exp_f32_e32 v3, s2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
; SI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
; SI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
-; SI-GISEL-NEXT: s_mov_b32 s10, -1
-; SI-GISEL-NEXT: s_mov_b32 s11, 0xf000
-; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-GISEL-NEXT: s_endpgm
;
; VI-SDAG-LABEL: s_exp2_v4f32:
@@ -774,24 +798,28 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
-; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, s4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v5, s6, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_exp_f32_e32 v5, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; VI-GISEL-NEXT: v_add_f32_e32 v2, s7, v2
-; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; VI-GISEL-NEXT: v_exp_f32_e32 v3, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v3, s4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
; VI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
@@ -847,24 +875,28 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s5, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, s4
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v5, s6, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, s0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s7, v2
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, s4
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
@@ -1820,10 +1852,14 @@ define float @v_exp2_f32_undef() {
; GCN-GISEL-LABEL: v_exp2_f32_undef:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
; GCN-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
-; GCN-GISEL-NEXT: v_add_f32_e64 v2, s4, 0
+; GCN-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GCN-GISEL-NEXT: v_add_f32_e64 v1, s4, 0
+; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
+; GCN-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GCN-GISEL-NEXT: v_mov_b32_e32 v2, s5
; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index a0b2d3b32b7957f..349c0c755b0d8f8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -59,6 +59,8 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -115,15 +117,19 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s0, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -177,6 +183,8 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
@@ -224,19 +232,21 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s3
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_mov_b32 v1, 0
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s3
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v1 :: v_dual_mov_b32 v1, 0
; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -375,6 +385,8 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6
; SI-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7
; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
@@ -388,6 +400,8 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2
; SI-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3
; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1]
@@ -458,11 +472,15 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v5, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v5, s0, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v3
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
@@ -477,10 +495,14 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v2
; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v5, s2, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
@@ -545,6 +567,8 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
@@ -558,6 +582,8 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2
; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1]
@@ -613,24 +639,29 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s2, v0 :: v_dual_mul_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, 0x3f317217, v0 :: v_dual_mul_f32 v3, 0x3f317217, v1
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v4, 0x3f317217, v0, -v2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3f317217, v1, -v3
; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v4, 0x3377d1cf, v0 :: v_dual_fmac_f32 v5, 0x3377d1cf, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_add_f32 v3, v3, v5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s4
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s5
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s4
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v1|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, s3, s2
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_sub_f32 v1, v1, v3
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -819,6 +850,8 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7
; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
@@ -827,15 +860,17 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_log_f32_e32 v6, v6
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v6
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; SI-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; SI-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9
+; SI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1
; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1]
@@ -844,6 +879,8 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6
; SI-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3
; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
@@ -934,49 +971,61 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s0, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v2, s[0:1]
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s5, v3
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s[0:1]
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4
+; VI-GISEL-NEXT: v_log_f32_e32 v4, v4
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x41b17218
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6
-; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v7, v3, v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v4
+; VI-GISEL-NEXT: v_sub_f32_e32 v7, v4, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v7, s2, v7
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v6, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v4|, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v6, s[2:3]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[0:1]
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_and_b32_e32 v4, 0xfffff000, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v6, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v4
; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v6
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s0, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s8
@@ -1053,6 +1102,8 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v1
@@ -1061,15 +1112,17 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1]
@@ -1078,6 +1131,8 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
@@ -1154,20 +1209,19 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x41b17218, s3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s2
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s4, v0 :: v_dual_mul_f32 v1, s5, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_fma_f32 v6, 0x3f317217, v0, -v3
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
@@ -1178,21 +1232,29 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v7, 0x3377d1cf, v1
; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x41b17218, s7
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x41b17218, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_add_f32_e32 v4, v4, v7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v8, 0x3377d1cf, v2 :: v_dual_mov_b32 v3, 0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v10
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v8 :: v_dual_sub_f32 v0, v0, v9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 0x41b17218, s3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s7
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s3, v4
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s5
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v1|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, s3, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3377d1cf, v2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v2|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v5
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -1436,6 +1498,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
@@ -1453,18 +1517,22 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc
; SI-GISEL-NEXT: v_mul_f32_e32 v9, s10, v9
; SI-GISEL-NEXT: v_log_f32_e32 v9, v9
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v9
-; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2
; SI-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8
-; SI-GISEL-NEXT: v_log_f32_e32 v3, v2
; SI-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10
; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v10
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v8
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, s0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2
+; SI-GISEL-NEXT: v_log_f32_e32 v3, v2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
@@ -1473,6 +1541,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; SI-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8
; SI-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4
; SI-GISEL-NEXT: v_add_f32_e32 v4, v8, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1]
@@ -1578,12 +1648,16 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
@@ -1598,31 +1672,39 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v6
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v7, s2, v7
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 1.0, v3, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v7
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
; VI-GISEL-NEXT: v_log_f32_e32 v7, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[0:1]
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v7
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
; VI-GISEL-NEXT: v_sub_f32_e32 v8, v7, v6
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v10, 0x3805fdf4, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
; VI-GISEL-NEXT: v_add_f32_e32 v9, v10, v9
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v9
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317000, v8
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; VI-GISEL-NEXT: v_add_f32_e32 v8, s0, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s0, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
+; VI-GISEL-NEXT: v_log_f32_e32 v3, v2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v6, s[2:3]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
@@ -1632,10 +1714,14 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v6
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; VI-GISEL-NEXT: v_add_f32_e32 v7, s2, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[0:1]
@@ -1726,6 +1812,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
@@ -1743,18 +1831,22 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc
; GFX900-GISEL-NEXT: v_mul_f32_e32 v9, s6, v9
; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v9
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v9
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8
-; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2
; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10
; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v10
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v8
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, s0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
@@ -1763,6 +1855,8 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8
; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4
; GFX900-GISEL-NEXT: v_add_f32_e32 v4, v8, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1]
@@ -1848,47 +1942,52 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s8
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x4f800000, s9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 0x41b17218, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s4, v0 :: v_dual_mul_f32 v1, s5, v1
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, s6, v2 :: v_dual_mul_f32 v3, s7, v3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 0x41b17218, s3
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x41b17218, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x41b17218, s9
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3f317217, v0 :: v_dual_mul_f32 v6, 0x3f317217, v1
+; GFX1100-GISEL-NEXT: v_dual_mul_f32 v4, 0x3f317217, v0 :: v_dual_mul_f32 v5, 0x3f317217, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v7, 0x3f317217, v2 :: v_dual_mul_f32 v8, 0x3f317217, v3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3f317217, v0, -v5
-; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3f317217, v1, -v6
+; GFX1100-GISEL-NEXT: v_dual_mul_f32 v6, 0x3f317217, v2 :: v_dual_mul_f32 v7, 0x3f317217, v3
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v9, 0x3f317217, v0, -v4
+; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3f317217, v1, -v5
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v7
-; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v8
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v10, 0x3377d1cf, v0 :: v_dual_fmac_f32 v11, 0x3377d1cf, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
+; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3f317217, v2, -v6
+; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3f317217, v3, -v7
+; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v9, 0x3377d1cf, v0 :: v_dual_fmac_f32 v10, 0x3377d1cf, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v7, v7, v12 :: v_dual_add_f32 v8, v8, v13
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v3, v3, v8 :: v_dual_sub_f32 v2, v2, v14
+; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v11, 0x3377d1cf, v2 :: v_dual_fmac_f32 v12, 0x3377d1cf, v3
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v4, v4, v9 :: v_dual_add_f32 v5, v5, v10
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v6, v6, v11 :: v_dual_add_f32 v7, v7, v12
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s9
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s6
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v1|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, s3, s2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v2|
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v8 :: v_dual_sub_f32 v1, v1, v13
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v3|
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, s5, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v3, v3, v15
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v2, v2, v14 :: v_dual_sub_f32 v3, v3, v9
; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -5577,10 +5676,12 @@ define float @v_log_f32_undef() {
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -5617,14 +5718,18 @@ define float @v_log_f32_undef() {
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -5659,10 +5764,12 @@ define float @v_log_f32_undef() {
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -5692,15 +5799,16 @@ define float @v_log_f32_undef() {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s0, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s0, s1
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -5744,10 +5852,12 @@ define float @v_log_f32_0() {
; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v4
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x41b17218
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -5782,14 +5892,18 @@ define float @v_log_f32_0() {
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s4, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x41b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -5822,10 +5936,12 @@ define float @v_log_f32_0() {
; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v4
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x41b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -5853,16 +5969,18 @@ define float @v_log_f32_0() {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-GISEL-NEXT: v_cmp_lt_f32_e64 s0, 0, 0x800000
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s0, s1
+; GFX1100-GISEL-NEXT: v_cmp_lt_f32_e64 s0, 0, 0x800000
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 5ba72612321a6ad..d432f3114b6d087 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -59,6 +59,8 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -115,15 +117,19 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s0, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -177,6 +183,8 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
@@ -224,19 +232,21 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s3
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_mov_b32 v1, 0
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s3
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v1 :: v_dual_mov_b32 v1, 0
; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -375,6 +385,8 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6
; SI-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7
; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
@@ -388,6 +400,8 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; SI-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2
; SI-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3
; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1]
@@ -458,11 +472,15 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: v_sub_f32_e32 v5, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v5
-; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v5, s0, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v3
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
@@ -477,10 +495,14 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v2
; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v5, s2, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v5
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1]
@@ -545,6 +567,8 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
@@ -558,6 +582,8 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2
; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1]
@@ -613,24 +639,29 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s2, v0 :: v_dual_mul_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, 0x3e9a209a, v0 :: v_dual_mul_f32 v3, 0x3e9a209a, v1
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v4, 0x3e9a209a, v0, -v2
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3e9a209a, v1, -v3
; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v4, 0x3284fbcf, v0 :: v_dual_fmac_f32 v5, 0x3284fbcf, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_add_f32 v3, v3, v5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s4
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s5
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s4
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s5
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s4
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v1|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, s3, s2
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_sub_f32 v1, v1, v3
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -819,6 +850,8 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7
; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
@@ -827,15 +860,17 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: v_log_f32_e32 v6, v6
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v6
-; SI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
; SI-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; SI-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9
+; SI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1
; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1]
@@ -844,6 +879,8 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6
; SI-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3
; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
@@ -934,49 +971,61 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s0, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v2, s[0:1]
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, s5, v3
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v2, s[0:1]
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s5, v4
+; VI-GISEL-NEXT: v_log_f32_e32 v4, v4
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x411a209b
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6
-; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v3
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
-; VI-GISEL-NEXT: v_sub_f32_e32 v7, v3, v6
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v4
+; VI-GISEL-NEXT: v_sub_f32_e32 v7, v4, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v7, s2, v7
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v6, s[2:3]
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[0:1]
-; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v2
-; VI-GISEL-NEXT: v_sub_f32_e32 v6, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v4|, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v6, s[2:3]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[0:1]
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_and_b32_e32 v4, 0xfffff000, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v6, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v4
; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v6
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v4
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s0, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v3
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s8
@@ -1053,6 +1102,8 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v1
@@ -1061,15 +1112,17 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v6
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1
; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s6, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1]
@@ -1078,6 +1131,8 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6
; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3
; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc
@@ -1154,20 +1209,19 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s3
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x411a209b, s3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s2
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s4, v0 :: v_dual_mul_f32 v1, s5, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_fma_f32 v6, 0x3e9a209a, v0, -v3
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
@@ -1178,21 +1232,29 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v7, 0x3284fbcf, v1
; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x411a209b, s7
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x411a209b, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_add_f32_e32 v4, v4, v7
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v8, 0x3284fbcf, v2 :: v_dual_mov_b32 v3, 0
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v10
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v8 :: v_dual_sub_f32 v0, v0, v9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 0x411a209b, s3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s7
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s3, v4
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s5
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v1|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, s3, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3284fbcf, v2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v2|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v5
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -1436,6 +1498,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1
; SI-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
@@ -1453,18 +1517,22 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc
; SI-GISEL-NEXT: v_mul_f32_e32 v9, s10, v9
; SI-GISEL-NEXT: v_log_f32_e32 v9, v9
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v9
-; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2
; SI-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8
-; SI-GISEL-NEXT: v_log_f32_e32 v3, v2
; SI-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10
; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v10
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v8
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, s0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2
+; SI-GISEL-NEXT: v_log_f32_e32 v3, v2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
@@ -1473,6 +1541,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; SI-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8
; SI-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4
; SI-GISEL-NEXT: v_add_f32_e32 v4, v8, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s2
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1]
@@ -1578,12 +1648,16 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
-; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, s0, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
@@ -1598,31 +1672,39 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v6
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
-; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v7, s2, v7
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 1.0, v3, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v7
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
; VI-GISEL-NEXT: v_log_f32_e32 v7, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[0:1]
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6
; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v7
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
; VI-GISEL-NEXT: v_sub_f32_e32 v8, v7, v6
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v10, 0x369a84fb, v6
-; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
; VI-GISEL-NEXT: v_add_f32_e32 v9, v10, v9
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v9
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a2000, v8
-; VI-GISEL-NEXT: v_log_f32_e32 v3, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9
+; VI-GISEL-NEXT: v_add_f32_e32 v8, s0, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s0, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
+; VI-GISEL-NEXT: v_log_f32_e32 v3, v2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v6, s[2:3]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
@@ -1632,10 +1714,14 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v6
; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v8
; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7
-; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; VI-GISEL-NEXT: v_add_f32_e32 v7, s2, v7
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v7
; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
-; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_add_f32_e32 v6, s2, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v6
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s2
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v4
; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[0:1]
@@ -1726,6 +1812,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1
; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s5, v2
@@ -1743,18 +1831,22 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc
; GFX900-GISEL-NEXT: v_mul_f32_e32 v9, s6, v9
; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v9
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v8
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1]
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8
; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v9
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8
-; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2
; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10
; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v10
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v8
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, s0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1]
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s7, v2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc
@@ -1763,6 +1855,8 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8
; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4
; GFX900-GISEL-NEXT: v_add_f32_e32 v4, v8, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, s2
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1]
@@ -1848,47 +1942,52 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s8
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x4f800000, s9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 0x411a209b, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s4, v0 :: v_dual_mul_f32 v1, s5, v1
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, s6, v2 :: v_dual_mul_f32 v3, s7, v3
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s3
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 0x411a209b, s3
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x411a209b, s8
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x411a209b, s9
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v0 :: v_dual_mul_f32 v6, 0x3e9a209a, v1
+; GFX1100-GISEL-NEXT: v_dual_mul_f32 v4, 0x3e9a209a, v0 :: v_dual_mul_f32 v5, 0x3e9a209a, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT: v_dual_mul_f32 v7, 0x3e9a209a, v2 :: v_dual_mul_f32 v8, 0x3e9a209a, v3
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3e9a209a, v0, -v5
-; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3e9a209a, v1, -v6
+; GFX1100-GISEL-NEXT: v_dual_mul_f32 v6, 0x3e9a209a, v2 :: v_dual_mul_f32 v7, 0x3e9a209a, v3
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v9, 0x3e9a209a, v0, -v4
+; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3e9a209a, v1, -v5
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v7
-; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v8
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v10, 0x3284fbcf, v0 :: v_dual_fmac_f32 v11, 0x3284fbcf, v1
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11
+; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3e9a209a, v2, -v6
+; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3e9a209a, v3, -v7
+; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v9, 0x3284fbcf, v0 :: v_dual_fmac_f32 v10, 0x3284fbcf, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_dual_add_f32 v7, v7, v12 :: v_dual_add_f32 v8, v8, v13
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v9
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v3, v3, v8 :: v_dual_sub_f32 v2, v2, v14
+; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v11, 0x3284fbcf, v2 :: v_dual_fmac_f32 v12, 0x3284fbcf, v3
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v4, v4, v9 :: v_dual_add_f32 v5, v5, v10
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v6, v6, v11 :: v_dual_add_f32 v7, v7, v12
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s9
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s6
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v1|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, s3, s2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v2|
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v8 :: v_dual_sub_f32 v1, v1, v13
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, s4, s2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v3|
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, s5, s2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v3, v3, v15
+; GFX1100-GISEL-NEXT: v_dual_sub_f32 v2, v2, v14 :: v_dual_sub_f32 v3, v3, v9
; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_nop 0
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -5577,10 +5676,12 @@ define float @v_log10_f32_undef() {
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -5617,14 +5718,18 @@ define float @v_log10_f32_undef() {
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -5659,10 +5764,12 @@ define float @v_log10_f32_undef() {
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -5692,15 +5799,16 @@ define float @v_log10_f32_undef() {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s0, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s0, s1
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -5744,10 +5852,12 @@ define float @v_log10_f32_0() {
; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v4
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
-; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x411a209b
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -5782,14 +5892,18 @@ define float @v_log10_f32_0() {
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
-; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, s4, v3
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-GISEL-NEXT: v_add_f32_e32 v2, s4, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x411a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -5822,10 +5936,12 @@ define float @v_log10_f32_0() {
; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v4
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v4, v2
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s4
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x411a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -5853,16 +5969,18 @@ define float @v_log10_f32_0() {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-GISEL-NEXT: v_cmp_lt_f32_e64 s0, 0, 0x800000
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s0, s1
+; GFX1100-GISEL-NEXT: v_cmp_lt_f32_e64 s0, 0, 0x800000
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
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