[llvm] [RISCV] Implement RISCVInstrInfo::getMemOperandsWithOffsetWidth (PR #73681)

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git-clang-format --diff 0783bf1cb3e47fc48813ee63f42d72b70d8cb792 bcf71140c2801ebb7c800bc8c8cc629769afb035 -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6c8c5db37e..6c5712dc79 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2202,25 +2202,26 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
 
   // Conservatively, only handle scalar loads/stores for now.
   switch (LdSt.getOpcode()) {
-    case RISCV::LB:
-    case RISCV::LBU:
-    case RISCV::SB:
-    case RISCV::LH:
-    case RISCV::LHU:
-    case RISCV::FLH:
-    case RISCV::SH:
-    case RISCV::FSH:
-    case RISCV::LW:
-    case RISCV::LWU:
-    case RISCV::FLW:
-    case RISCV::SW:
-    case RISCV::FSW:
-    case RISCV::LD:
-    case RISCV::FLD:
-    case RISCV::SD:
-    case RISCV::FSD:
-      break;
-    default: return false;
+  case RISCV::LB:
+  case RISCV::LBU:
+  case RISCV::SB:
+  case RISCV::LH:
+  case RISCV::LHU:
+  case RISCV::FLH:
+  case RISCV::SH:
+  case RISCV::FSH:
+  case RISCV::LW:
+  case RISCV::LWU:
+  case RISCV::FLW:
+  case RISCV::SW:
+  case RISCV::FSW:
+  case RISCV::LD:
+  case RISCV::FLD:
+  case RISCV::SD:
+  case RISCV::FSD:
+    break;
+  default:
+    return false;
   }
   const MachineOperand *BaseOp;
   OffsetIsScalable = false;

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https://github.com/llvm/llvm-project/pull/73681