[llvm] [RISCV] Work on subreg for insert_vector_elt when vlen is known (#72666) (PR #73680)
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Tue Nov 28 10:21:26 PST 2023
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git-clang-format --diff 0783bf1cb3e47fc48813ee63f42d72b70d8cb792 cff94d4b078b04b26855f59e62bf439a8b2f2b1d -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 72b2e5e78c..d7f5771d5c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7747,8 +7747,8 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
if (auto *IdxC = dyn_cast<ConstantSDNode>(Idx)) {
const unsigned OrigIdx = IdxC->getZExtValue();
// Do we know an upper bound on LMUL?
- if (auto ShrunkVT = getSmallestVTForIndex(ContainerVT, OrigIdx,
- DL, DAG, Subtarget)) {
+ if (auto ShrunkVT =
+ getSmallestVTForIndex(ContainerVT, OrigIdx, DL, DAG, Subtarget)) {
ContainerVT = *ShrunkVT;
AlignedIdx = DAG.getVectorIdxConstant(0, DL);
}
@@ -7772,8 +7772,8 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
}
if (AlignedIdx)
- Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT, Vec,
- AlignedIdx);
+ Vec =
+ DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT, Vec, AlignedIdx);
}
MVT XLenVT = Subtarget.getXLenVT();
@@ -7839,9 +7839,8 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
ValInVec = DAG.getBitcast(ContainerVT, ValInVec);
if (AlignedIdx)
- ValInVec =
- DAG.getNode(ISD::INSERT_SUBVECTOR, DL, OrigContainerVT, OrigVec,
- ValInVec, AlignedIdx);
+ ValInVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, OrigContainerVT,
+ OrigVec, ValInVec, AlignedIdx);
if (!VecVT.isFixedLengthVector())
return ValInVec;
return convertFromScalableVector(VecVT, ValInVec, DAG, Subtarget);
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https://github.com/llvm/llvm-project/pull/73680
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