[llvm] [IRBuilder] Limit created masked load/store alignment to valid 32bit values (PR #73647)

Guillaume Chatelet via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 28 08:13:39 PST 2023

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https://github.com/gchatelet edited https://github.com/llvm/llvm-project/pull/73647

Previous message: [llvm] [IRBuilder] Limit created masked load/store alignment to valid 32bit values (PR #73647)
Next message: [llvm] [AMDGPU] Lazily emit waitcnts on function entry (PR #73122)
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